71T75902S75PFG Datasheet 71T75902S75PFGI, 71T75902S75PFG, 71T75902S85BGG | P10-P12

6.4210

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

NOTES:

1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

2. H = High; L = Low; X = Don't Care; Z = High Impedence.

Device Operation - Showing Mixed Load, Burst,

Deselect and NOOP Cycles

(2)

Cycle

Address

ADV/

(1 )

CEN BW

I/O

Comments

HL LLXXD

Load read

n+1 X X H XLXLQ

Burst read

n+2 A

HL LLXLQ

0+1

Load read

n+3 X X L H L X L Q

Deselect or STOP

n+4 X X H X L X X Z NOOP

n+5 A

H L L L X X Z Load read

n+6 X X H XLXLQ

Burst read

n+7 X X L H L X L Q

2+1

Deselect or STOP

n+8 A

L L LLLXZLoad write

n+9 X X H X L L X D

Burst write

n+10 A

L L LLLXD

3+1

Load write

n+11 X X L H L X X D

Deselect or STOP

n+12 X X H X L X X Z NOOP

n+13 A

L L LLLXZLoad write

n+14 A

HL LLXXD

Load read

n+15 A

L L LLLLQ

Load write

n+16 X X H X L L X D

Burst write

n+17 A

HL LLXXD

7+1

Load read

n+18 X X H X L X L Q

Burst read

n+19 A

L L LLLLQ

8+1

Load write

5319 tbl 12

6.42

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Read Operation

(1)

Burst Write Operation

(1)

Burst Read Operation

(1)

Write Operation

(1)

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Cycle

Address

ADV/

(2 )

CEN BW

I/O

Comments

H L L L X X X Address and Control meet setup

n+1 X X X XXXLQ

Contents of Address A

Read Out

5319 tbl 13

Cycle

Address

ADV/

(2 )

CEN BW

I/O

Comments

H L L L X X X Address and Control meet setup

n+1 X X H XLXLQ

Address A

Read Out, Inc. Count

n+2 X X H XLXLQ

0+1

Address A

0+1

Read Out, Inc. Count

n+3 X X H XLXLQ

0+2

Address A

0+2

Read Out, Inc. Count

n+4 X X H XLXLQ

0+3

Address A

0+3

Read Out, Load A

n+5 A

HL LLXLQ

Address A

Read Out, Inc. Count

n+6 X X H XLXLQ

Address A

Read Out, Inc. Count

n+7 A

HL LLXLQ

1+1

Address A

1+1

Read Out, Load A

5319 tbl 14

Cycle

Address

ADV/

(2 )

CEN BW

I/O

Comments

L L L L L X X Address and Control meet setup

n+1 X X X X L X X D

Write to Address A

5319 tbl 15

Cycle

Address

ADV/

(2 )

CEN BW

I/O

Comments

L L L L L X X Address and Control meet setup

n+1 X X H X L L X D

Address A

Write, Inc. Count

n+2 X X H X L L X D

0+1

Address A

0+1

Write, Inc. Count

n+3 X X H X L L X D

0+2

Address A

0+2

Write, Inc. Count

n+4 X X H X L L X D

0+3

Address A

0+3

Write, Load A

n+5 A

L L LLLXD

Address A

Write, Inc. Count

n+6 X X H X L L X D

Address A

Write, Inc. Count

n+7 A

L L LLLXD

1+1

Address A

1+1

Write, Load A

5319 tbl 16

6.4212

IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Read Operation with Clock Enable Used

(1)

Write Operation with Clock Enable Used

(1)

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Cycle

Address

ADV/

(2 )

CEN BW

I/O

Comments

H L L L X X X Address A

and Control meet setup

n+1 X X X X H X X X Clock n+1 Ignored

n+2 A

HL LLXLQ

Address A

Read out, Load A

n+3 X X X X H X L Q

Clock Ignored. Data Q

is on the bus.

n+4 X X X X H X L Q

Clock Ignored. Data Q

is on the bus.

n+5 A

HL LLXLQ

Address A

Read out, Load A

n+6 A

HL LLXLQ

Address A

Read out, Load A

n+7 A

HL LLXLQ

Address A

Read out, Load A

5319 tbl 17

Cycle

Address

ADV/

(2 )

CEN BW

I/O

Comments

L L L L L X X Address A

and Control meet setup.

n+1 X X X X H X X X Clock n+1 Ignored.

n+2 A

L L LLLXD

Write data D

, Load A

n+3 X X X X H X X X Clock Ignored.

n+4 X X X X H X X X Clock Ignored.

n+5 A

L L LLLXD

Write Data D

, Load A

n+6 A

L L LLLXD

Write Data D

, Load A

n+7 A

L L LLLXD

Write Data D

, Load A

5319 tbl 18

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

71T75902S75PFG

Mfr. #:

Buy 71T75902S75PFG

Manufacturer:

IDT

Description:

SRAM X18 18M 2.5V CORE ZBT SLO

Lifecycle:

New from this manufacturer.

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71T75902S75PFG

71T75902S75PFG

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