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71T75902S75PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
6.42
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Chip Enable Used
(1)
Write Operation with Chip Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD
CE
1
(2 )
CEN BW
x
OE
I/O
(3 )
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X Z Deselected.
n+2 A
0
H L L L X X Z Address A
0
and Control meet setup.
n+3 X X L H L X L Q
0
Address A
0
read out, Deselected.
n+4 A
1
H L L L X X Z Address A
1
and Control meet setup.
n+5 X X L H L X L Q
1
Address A
1
read out, Deselected.
n+6 X X L H L X X Z Deselected.
n+7 A
2
H L L L X X Z Address A
2
and Control meet setup.
n+8 X X L H L X L Q
2
Address A
2
read out, Deselected.
n+9 X X L H L X X Z Deselected.
5319 tbl 19
Cycle
Address
R/
W
ADV/
LD
CE
(2 )
CEN BW
x
OE
I/O
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X Z Deselected.
n+2 A
0
L L L L L X Z Address A
0
and Control meet setup
n+3 X X L H L X X D
0
Data D
0
Write In, Deselected.
n+4 A
1
L L L L L X Z Address A
1
and Control meet setup
n+5 X X L H L X X D
1
Data D
1
Write In, Deselected.
n+6 X X L H L X X Z Deselected.
n+7 A
2
L L L L L X Z Address A
2
and Control meet setup
n+8 X X L H L X X D
2
Data D
2
Write In, Deselected.
n+9 X X L H L X X Z Deselected.
5319 tbl 20
6.4214
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(VDD = 2.5V±5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load
AC Test Conditions
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(VDD = 2.5V±5%)
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|I
L
I
| Input Leakage Current V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LI
|
LBO
, JTAG and ZZ Input Leakage Current
(1 )
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
CC
___
5µA
V
OL
Output Low Voltage I
OL
= +6mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -6mA, V
DD
= Min. 2.0
___
V
5319 tbl 21
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l
Ind
Com'l
Ind
Com'l
Ind
I
DD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/
LD
= X, V
DD
= Max.,
V
IN
>
V
IH
or
<
V
IL
, f = f
MAX
(2)
275
295
250
270
225
245
mA
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
>
V
HD
or
<
V
LD
,
f = 0
(2,3)
40
60
40
60
40
60
mA
I
SB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
>
V
HD
or
<
V
LD
,
f = f
MAX
(2,3)
105
125
100
120
95
115
mA
I
SB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN
>
V
IH
, V
DD
= Max.,
V
IN
>
V
HD
or
<
V
LD
, f = f
MAX
(2,3)
60
80
60
80
60
80
mA
I
ZZ
Full Sleep Mode
Supply Current
Device Selected, Outputs Open,
CEN
<
V
IH
, V
DD
= Max., ZZ
>
V
HD
V
IN
>
V
HD
or
<
V
LD
, f = f
MAX
(2,3)
40
60
40
60
40
60
mA
5319 tbl 22
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
0 to 2.5V
2ns
(V
DDQ/ 2
)
(V
DD Q /2
)
Figure 1
5319 tbl 23
1
2
3
4
20 30 50 100 200
∆t
CD
(Typical, ns)
Capacitance (pF)
80
5
6
5319 drw 05
•
•
•
•
•
,
V
DDQ
/2
50Ω
I/O
Z
0
=50Ω
5319 drw 04
,
6.42
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
15
AC Electrical Characteristics
(VDD = 2.5V±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 2.375V).
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
CYC
Clock Cycle Time 10
____
10.5
____
11
____
ns
t
CH
(1 )
Clock High Pulse Width 2.5
____
2.7
____
3.0
____
ns
t
CL
(1 )
Clock Low Pulse Width 2.5
____
2.7
____
3.0
____
ns
Output Parameters
t
CD
Clock High to Valid Data
____
7.5
____
8
____
8.5 ns
t
CD C
Clock High to Data Change 2
____
2
____
2
____
ns
t
CL Z
(2 , 3 ,4 )
Clock High to Output Active 3
____
3
____
3
____
ns
t
CHZ
(2 , 3 ,4 )
Clock High to Data High-Z
____
5
____
5
____
5ns
t
OE
Output Enable Access Time
____
5
____
5
____
5ns
t
OLZ
(2,3)
Output Enable Low to Data Active 0
____
0
____
0
____
ns
t
OHZ
(2,3)
Output Enable High to Data High-Z
____
5
____
5
____
5ns
Set Up Times
t
SE
Clock Enable Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SA
Address Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SD
Data In Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SW
Read/Write (R/
W
) Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SADV
Advance/Load (ADV/
LD
) Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SC
Chip Enable/Select Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SB
Byte Write Enable (
BW
x) Setup Time 2.0
____
2.0
____
2.0
____
ns
Hold Times
t
HE
Clock Enable Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HA
Address Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HW
Read/Write (R/
W
) Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HADV
Advance/Load (ADV/
LD
) Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HB
Byte Write Enable (
BW
x) Hold Time 0.5
____
0.5
____
0.5
____
ns
5319 tbl 24
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

71T75902S75PFG

Mfr. #:
Buy 71T75902S75PFG
Manufacturer:
IDT
Description:
SRAM X18 18M 2.5V CORE ZBT SLO
Lifecycle:
New from this manufacturer.
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