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71T75902S75PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
6.42
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
7
Top View
Pin Configuration  512K x 36, 119 BGA
(1,2,3,4)
Pin Configurations  1M x 18, 119 BGA
(1,2,3,4)
NOTES:
1. Pins R5 and J5 do not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pin J3 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several
settings are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST)
U2, U3, U4 and U6 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
4. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device).
5. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
Top View
1
2
3
4
5
6
7
A
V
DDQ
A
6
A
4
A
19
A
8
A
16
V
DDQ
B
NC
CE
2
A
3
ADV/
LD
A
9
CE
2
NC
C
NC
A
7
A
2
V
DD
A
13
A
17
NC
D
I/O
8
NC
V
SS
NC
V
SS
I/O
P1
NC
E
NC
I/O
9
V
SS
CE
1
V
SS
NC
I/O
7
F
V
DDQ
NC
V
SS
OE
V
SS
I/O
6
V
DDQ
G
NC
I/O
10
BW
2
A
18
V
SS
NC
I/O
5
H
I/O
11
NC
V
SS
R/
W
V
SS
I/O
4
NC
J
V
DDQ
V
DD
V
DD
(2)
V
DD
V
SS
(1)
V
DD
V
DDQ
K
NC
I/O
12
V
SS
CLK
V
SS
NC
I/O
3
L
I/O
13
NC
V
SS
NC
BW
1
I/O
2
NC
M
V
DDQ
I/O
14
V
SS
CEN
V
SS
NC
V
DDQ
N
I/O
15
NC
V
SS
A
1
V
SS
I/O
1
NC
P
NC
I/O
P2
V
SS
A
0
V
SS
NC
I/O
0
R
NC
A
5
LBO
V
DD
V
SS
(1)
A
12
NC
T
NC
A
10
A
15
NC
(4)
A
14
A
11
ZZ
U
V
DDQ
NC/TMS
(3)
NC/TDI
(3)
NC/TCK
(3)
NC/TDO
(3)
NC/
TRS T
(3, 5 )
V
DDQ
5319 tb l 2 5a
1
2
3
4
5
6
7
A
V
DDQ
A
6
A
4
A
18
A
8
A
16
V
DDQ
B
NC
CE
2
A
3
ADV/
LD
A
9
CE
2
NC
C
NC
A
7
A
2
V
DD
A
12
A
15
NC
D
I/O
16
I/O
P3
V
SS
NC
V
SS
I/O
P2
I/O
15
E
I/O
17
I/O
18
V
SS
CE
1
V
SS
I/O
13
I/O
14
F
V
DDQ
I/O
19
V
SS
OE
V
SS
I/O
12
V
DDQ
G
I/O
20
I/O
21
BW
3
A
17
BW
2
I/O
11
I/O
10
H
I/O
22
I/O
23
V
SS
R/
W
V
SS
I/O
9
I/O
8
J
V
DDQ
V
DD
V
DD
(2)
V
DD
V
SS
(1)
V
DD
V
DDQ
K
I/O
24
I/O
26
V
SS
CLK
V
SS
I/O
6
I/O
7
L
I/O
25
I/O
27
BW
4
NC
BW
1
I/O
4
I/O
5
M
V
DDQ
I/O
28
V
SS
CEN
V
SS
I/O
3
V
DDQ
N
I/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
P
I/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
P1
I/O
0
R
NC
A
5
LBO
V
DD
V
SS
(1)
A
13
NC
T
NC
NC
A
10
A
11
A
14
NC
(4)
ZZ
U
V
DDQ
NC/TMS
(3)
NC/TDI
(3)
NC/TCK
(3)
NC/TDO
(3)
NC/
TRS T
(3, 5 )
V
DDQ
5319 tbl 25
6.428
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Partial Truth Table for Writes
(1)
Synchronous Truth Table
(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
CEN
R/
W
CE
1
,
CE
2
(5 )
ADV/
LD
BW
x
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
L L L L Valid External X LOAD WRITE D
(7)
L H L L X External X LOAD READ Q
(7 )
L X X H Valid Internal LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)
(2)
D
(7 )
L X X H X Internal LOAD READ /
BURST READ
BURST READ
(Advance burst counter)
(2)
Q
(7 )
L X H L X X X DESELECT or STOP
(3 )
HIZ
L X X H X X DESELECT / NOOP NOOP HIZ
H X X X X X X SUSPEND
(4 )
Previous Value
5319 tbl 08
OPERATION
R/
W
BW
1
BW
2
BW
3
(3 )
BW
4
(3 )
READ HXXXX
WRITE ALL BYTES LLLLL
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2 )
LLHHH
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2 )
LHLHH
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
LHHLH
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
LHHHL
NO WRITE LHHHH
5319 tbl 09
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1 )
11100100
5319 tbl 10
6.42
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
9
Functional Timing Diagram
(1)
Linear Burst Sequence Table (LBO=VSS)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1 )
11000110
5319 tbl 11
n+29
A29
C29
D/Q28
ADDRESS
(A
0
-A
18
)
CONTROL
(R/W, ADV/LD, BWx)
DATA
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q29
n+31
A31
C31
D/Q30
n+32
A32
C32
D/Q31
n+33
A33
C33
D/Q32
n+34
A34
C34
D/Q33
n+35
A35
C35
D/Q34
n+36
A36
C36
D/Q35
n+37
A37
C37
D/Q36
5319 drw 03
(2)
(2)
(2)
,
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

71T75902S75PFG

Mfr. #:
Buy 71T75902S75PFG
Manufacturer:
IDT
Description:
SRAM X18 18M 2.5V CORE ZBT SLO
Lifecycle:
New from this manufacturer.
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