ASAHI KASEI [AK8411]
MS0457-E-00 2006/05
11
Analog Characteristics
(AVDD=3.3V, DRVDD=3.3V, MCLK=40MHz, Single Edge Mode, Ta=25°C,
unless otherwise specified)
Item Min. Typ. Max. Unit Note
Reference Voltage
VCOM voltage
VRP voltage
VRN voltage
1.4
1.9
0.9
1.5
2.0
1.0
1.6
2.1
1.1
V
V
V
Analog Input
Maximum signal input level 1.98 V
p-p
–0.7 0 0.7 dB At DC mode (Note 1) Absolute gain
–1.45 –0.45 0.55 dB At CDS mode (Note 1)
Sampling rate 1 5 MSPS
Input reference level 0 1.1 1.5 V At DC mode
VCLP Input resistance 10 60 kΩ At DC mode
Signal input range 0 AVDD V At DC mode (Note 2)
Clamp level (VCLP voltage ) 1.95 2.05 2.15 V At CDS mode
Clamp resister 7 10 kΩ At CDS mode
Black level correction DAC
Resolution 8 bit (Note 3)
Correctable range ±215 ±240 ±265 mV (Note 4)
Internal offset voltage –50 50 mV (Note 5)
PGA (Programmable Gain Amp.) circuit
Resolution 6 bit
0 dB Minimum gain
Maximum gain
12.9 13.9 14.9 dB (Note 6)
Video ADC
Resolution 16 bit
Differential Non-linearity –16 +16 LSB
Integral Non-linearity ±32 LSB
Noise
5 LSB
rms
PGA min. Output noise
15
LSB
rms
PGA max.
Power Consumption
21.5 31.5 mA At DC mode (Note 7)
24.5 34.5 mA At CDS mode (Note 7)
Analog part
power dissipations
0.1 mA At Power down (Note 8)
Digital output driver power
dissipation
3 10 mA (Note 9)
(Note 1) 0dB is defined at the gain where ADC output reaches its full-scale when 1.98Vpp
signal is input with PGA setting at 00h.
(Note 2) CISIN input signal must be in this range which is referenced to AVSS.
(Note 3) Monotonicity guaranteed.
(Note 4)
±50 mV of the total correctable range is used for internal offset adjustment.
(Note 5) It defines that a boundary point of ADC output codes between 0000h and 0001h
exists within
±50mV range of the offset adjustment DAC setting when 1.1V is fed on
CISIN & VCLP pins in DC Direct Coupled mode, and when PGA gain is set to 0dB.
