ASAHI KASEI [AK8411]
MS0457-E-00 2006/05
4
Functional Description
Main Clock (MCLK)
The AK8411 has two clock modes, Single Edge Mode and Double Edge Mode. A required
clock frequency differs in each mode. In the Single Edge mode, the required MCLK frequency
is 8 times of the Pixel clock rate and in the Double Edge mode, it is 4 times of the Pixel clock
rate. When to change MCLK frequency, a time required from frequency change to valid data
output is 10 ms maximum.
Sampling Timing Pulse (TSMP)
TSMP is a pixel-period-equivalent input pulse to decide sampling timing of input signal. As
MCLK and TSMP are also used to generate internal common voltage, it takes 10 ms
maximum to output valid data upon stabilization of internal common voltage after re-start of
MCLK and TSMP when MCLK or TSMP is stopped longer than 2000 ns. When the stopped
time of MCLK or TSMP is equal to or shorter than 2000 ns, a valid data is output right after
the recovery of MCLK or TSMP application.
Clamp Circuit
Circuit to pull-in the feed-through level of CCD signal to VCLP voltage so that CCD signal to
be input is set within the input range of Sample & Hold circuit. This circuit is enabled at
CDS mode operation.
Sampling Pulses SHD, SHR (internal pulses)
SHD is an internal pulse to sample data level of CIS signal. CIS signal is sampled at the
falling edge of SHD. There are two types of sampling modes. One is MCLK Synchronous
Sampling Mode where SHD is internally generated from MCLK and TSMP, and the other is
TSMP Sampling Mode where TSMP is directly used as SHD as is. SHR is a pulse to sample
feed-through level of CIS signal in CDS mode operation. CIS signal is sampled at the falling
edge of SHR. SHR is also used to control clamp switch. Clamp switch is ON (Close) at SHR =
High and Clamp switch is OFF (Open) at SHR = Low.
