ASAHI KASEI [AK8411]
MS0457-E-00 2006/05
9
MCLK
TSMP
SHR
(Internal)
R0B3~B2=
00b
01b
10b
11b
Data Level Sampling
Feed through Level Samplin
D15
D14
D13 D11D9D7D5D3D1
D12 D10D8D6D4D2D0
D15 D13 D11 D9 D7 D5 D3 D1
D14 D12 D10 D8 D6 D4 D2 D0
D5 D3 D1
D4 D2 D0
D15
D14
D13
D12
D1
D0
CISIN
SHD
(Internal)
Fig. 8 Sampling Timing and ADC Output
( in Double Edge, TSMP Sampling Mode )
Power-On-Reset
VDD
RESETB
AK8411
100kΩ
0.33µF
VDD
RESETB
3.135V
VDD rising time
max. 10ms
Register can be written
after 100ms later
max. 100ms
Fig. 9 Power-On-Reset
At the power-on, Power-On-Reset must be executed by using RESETB pin. When a 0.33 uF
external capacitor on RESETB pin is used, the rise time of AVDD must be shorter than 10
ms in order to assure proper Power-On-Reset operation. Maximum time from AVDD
power-on to the release from Power-On-Reset is 100 ms. Registers should be written after
waiting for longer than 100 ms after AVDD power-on.
As electric charge is retained in the external capacitor even after AVDD is made to 0V,
voltage on RESETB pin does not go to 0V immediately. If AVDD is powered-up again before
RESETB pin returns to 0V, a proper Power-On-Reset operation is not made. In order to
assure proper Power-On-Reset operation when to power-up AVDD again, it is required that
AVDD time to be kept at 0V is longer than 300 ms. If the 300 ms AVDD time to be kept at 0V,
is not obtainable, the device must be reset by applying a low pulse externally on RESETB
pin.
