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AK8411VT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
ASAHI KASEI [AK8411]
MS0457-E-00 2006/05
13
MCLK
TSMP
0.7AVDD
0.7AVDD
1 (T)
4
3
SHD (Internal)
CISIN
5
Sample Point
0.5AVDD
2 2
0.7AVDD
0.3AVDD
0.3AVDD
43
7
Fig. 10 Sampling Timing (in DC Direct Coupled, Single Edge Mode)
MCL
K
TSMP
0.5AVDD
1 2
SHD (Internal)
CISIN
5
Sample Point
SHR (Internal)
6
Sample Point
2
0.3AVDD
0.7AVDD
0.7AVDD
43
0.3AVDD
43
7
Fig. 11 Sampling Timing (in CDS, Single Edge Mode)
SHD (Internal)
CISIN
5
Sample Point
MCLK
TSMP
0.7AVDD
0.7AVDD
1 (T)
4
3
0.5AVDD
2 2
0.7AVDD
0.3AVDD
0.3AVDD
43
7
Fig. 12 Sampling Timing (in DC Direct Coupled, Double Edge Mode)
ASAHI KASEI [AK8411]
MS0457-E-00 2006/05
14
SHD (Internal)
CISIN
5
Sample Point
SHR (Internal)
6
Sample Point
MCLK
TSMP
0.7AVDD
0.7AVDD
1 (T)
4
3
0.5AVDD
2 2
0.7AVDD
0.3AVDD
0.3AVDD
43
7
Fig. 13 Sampling Timing (in CDS, Double Edge Mode)
MCL
K
D0, D1
0.7AVDD
0.7DRVDD
8
0.3AVDD
0.3 DRVDD
Fig. 14 Data Output Timing (Single Edge Mode)
MCL
K
D0, D1
0.7AVDD
0.7DRVDD
8
0.3AVDD
0.3DRVDD
8
Fig. 15 Data Output Timing ( Double Edge Mode )
RESETB
10
0.3AVDD 0.3AVDD
Fig. 16 Reset Pulse Width
ASAHI KASEI [AK8411]
MS0457-E-00 2006/05
15
MCLK
TSMP
SHD
(Internal)
CISIN
n+5 n+4 n+3n+2n+1 n
D1
D0
n−4 n
−
3 n
−
2 n
−
1 n n−5
n−5 n−4 n
−
3 n
−
2 n
−
1 n
Fig. 17 Pipeline Delay (in Single Edge Mode)
MCLK
TSMP
SHD
(Internal)
CISIN
n+5 n+4 n+3n+2n+1 n
D1
D0
n−4 n
−
3 n
−
2 n
−
1 n n−5
n−5 n−4 n
−
3 n
−
2 n
−
1 n
Fig. 18 Pipeline Delay (in Double Edge Mode)
Data are output in the same Pipeline Delay time both in DC Direct Coupled Mode and CDS
Mode which is referenced to TSMP.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AK8411VT

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Description:
IC ADC 16BIT 5MSPS 1CH 16TSSOP
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