XR21V1410
10
1-CH FULL-SPEED USB UART
REV. 1.4.0
1.5.7 Automatic XON/XOFF Software Flow Control
When software flow control is enabled, the V1410 compares the receive data characters with the programmed
Xon or Xoff characters. If the received character matches the programmed Xoff character, the V1410 will halt
transmission as soon as the current character has completed transmission. Data transmission is resumed
when a received character matches the Xon character. Software flow control is enabled when
FLOW_CONTROL[2:0] = ’010’.
1.5.8 Auto RS-485 Half-Duplex Control
The Auto RS-485 Half-Duplex Control feature changes the behavior of the GPIO5/RTS#/RS485 pin when
enabled by the GPIO_MODE register bits 2-0. See ”Section 3.3.12, GPIO_MODE Register Description
(Read/Write)” on page 22. The FLOW_CONTROL register must also be set appropriately for use in multidrop
applications. See ”Section 3.3.6, FLOW_CONTROL Register Description (Read/Write)” on page 19. If
enabled, the transmitter automatically asserts the GPIO5/RTS#/RS485 output prior to sending the data. By
default, it de-asserts GPIO5/RTS#/RS485 following the last stop bit of the last character that has been
transmitted, but the RS485_DELAY register may be used to delay the deassertion. The polarity of the GPIO5/
RTS#/RS485 signal may also be modified using the GPIO_MODE register bit 3.
1.5.9 Multidrop Mode with address matching
The V1410 device has two address matching modes which are also set by the flow control register using
modes 3 and 4. These modes are intended for a multi-drop network application. In these modes, the
XON_CHAR register holds a unicast address and the XOFF_CHAR holds a multicast address. A unicast
address is used by a transmitting master to broadcast an address to all attached slave devices that is intended
for only one slave device. A multicast address is used to broadcast an address intended for more than one
recipient device. Each attached slave device should have a unique unicast address value stored in the
XON_CHAR register, while multiple slaves may have the same multicast adderss stored in the XOFF_CHAR
register. An address match occurs when an address byte (9th bit or parity bit is ’1’) is received that matches the
value stored in either the XON_CHAR or XOFF_CHAR register.
1.5.9.1 Receiver
If an address match occurs in either flow control mode 3 or 4, the address byte will not be loaded into the RX
FIFO, but all subsequent data bytes will be loaded into the RX FIFO. The UART Receiver will automatically be
disabled when an address byte is received that does not match the values in the XON_CHAR or XOFF_CHAR
register.
1.5.9.2 Transmitter
In flow control mode 3, the UART transmitter is always enabled, irrespective of the Rx address match. In flow
control mode 4, the UART transmitter will only be enabled if there is an Rx address match.
1.5.10 Programmable Turn-Around Delay
By default, the GPIO5/RTS#/RS485 pin will be de-asserted immediately after the stop bit of the last byte has
been shifted when auto RS-485 half-duplex control is enabled by the GPIO_MODE register. However, this
may not be ideal for systems where the signal needs to propagate over long cables. Therefore, the de-
assertion of GPIO5/RTS#/RS485 pin can be delayed from 1 to 15 bit times via the RS485_DELAY register to
allow for the data to reach distant UARTs.
1.5.11 Half-Duplex Mode
Half-duplex mode is enabled when FLOW_CONTROL[3] = 1. In this mode, the UART will ignore any data on
the RX input when the UART is transmitting data.
1.5.12 USB Suspend
All USB peripheral devices must support the USB suspend mode. Per USB standard, the V1410 device will
begin to enter the Suspend state if it does not detect any activity (including Start of Frame or SOF packets) on
its USB data lines for 3 ms. The device must then reduce power consumption from VBUS power within the
next 7 ms to the allowed limit of 2.5 mA for the suspended state. Note that in this context, the "device" is all
circuitry (including the V1410) that draws power from the host VBUS.
