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XR21V1410IL16-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
XR21V1410
22
1-CH FULL-SPEED USB UART
REV. 1.4.0
3.3.12 GPIO_MODE Register Description (Read/Write)
GPIO_MODE[2:0]: GPIO Mode Select
There are 4 modes of operation for the GPIOs. The descriptions can be found in “Section 1.5, UART” on
page 7.
GPIO_MODE[3]: RS485 Polarity
•
Logic 0 = GPIO5/RTS#/RS485 Low for TX
•
Logic 1 = GPIO5/RTS#/RS485 High for TX
GPIO_MODE[7:4]: Reserved
These register bits are reserved. When writing to these bits, the value should be ’0’. When reading from these
bits, they are undefined and should be ignored.
3.3.13 GPIO_DIRECTION Register Description (Read/Write)
This register controls the direction of pins configured as GPIO. (Pins configured for UART functions via the
GPIO_MODE register, e.g. RTS# are not controlled or reported in the GPIO_DIRECTION register.)
GPIO_DIRECTION[5:0]: GPIOx Direction
•
Logic 0 = GPIOx is an input.
•
Logic 1 = GPIOx is an output.
GPIO_DIRECTION[7:6]: Reserved
These register bits are reserved and should be ’0’.
3.3.14 GPIO_INT_MASK Register Description (Read/Write)
Enables / disables generation of a USB interrupt packet at the change of state of GPIO pins when they are
configured as inputs.
GPIO_INT_MASK[5:0]: GPIOx Interrupt Mask
•
Logic 0 = A change on this input causes the device to generate an interrupt packet.
•
Logic 1 = A change on this input does not cause the device to generate an interrupt packet.
GPIO_INT_MASK[7:6]: Reserved
These register bits are reserved and should be ’0’.
T
ABLE
14: GPIO M
ODES
BITS
[2:0]
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 M
ODE
D
ESCRIPTION
000 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO Mode, All GPIO pins available as GPIO
001 GPIO0 GPIO1 GPIO2 GPIO3 CTS# RTS# GPIO4 and GPIO5 used for Auto RTS/CTS HW
Flow Control
010 GPIO0 GPIO1 DSR# DTR# GPIO4 GPIO5 GPIO2 and GPIO3 used for Auto DTR/DSR HW
Flow Control
011 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 RS485 GPIO5 used for auto RS-485 half-duplex control
100 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 RS485 GPIO5 used for auto RS-485 half-duplex control
after address match (See FLOW_CONTROL
mode 4).
XR21V1410
23
REV. 1.4.0
1-CH FULL-SPEED USB UART
3.3.15 GPIO_SET Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output high. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.16 GPIO_CLEAR Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output low. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.17 GPIO_STATUS Register Description (Read-Only)
This register reports the current state of the GPIO pin.
3.4 UART Custom Registers
3.4.1 CUSTOM Register Description (Read/Write)
This register controls the bMaxPacketSize and enables the Wide mode functionality for the UART.
CUSTOM[0]: Enable wide mode
•
Logic 0 = Normal (7, 8 or 9 bit data) mode
•
Logic 1 = Wide mode - See “Section 1.5.1.1, Wide Mode Transmit” on page 7, “Section 1.5.2.3, Wide
mode receive operation with 7 or 8-bit data” on page 8 and “Section 1.5.2.4, Wide mode receive
operation with 9-bit data” on page 8.
CUSTOM[1]: Max Packet Size
•
Logic 0 = bMaxPacketSize = 64 bytes
•
Logic 1 = bMaxPacketSize = 63 bytes (this bit is automatically set to ’1’ if the XR21V1410 receives a
CDC_ACM USB command)
CUSTOM[7:2]: Reserved
These bits are reserved and should remain ’0’
3.4.2 LOW_LATENCY Register Description (Read/Write)
This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud
rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this
register following any desired baud rate setting change.
LOW_LATENCY[0]: Enable Low Latency mode
•
Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
•
Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO.
LOW_LATENCY[7:1]: Reserved
These bits are reserved and should remain ’0’.
T
ABLE
15: UART C
USTOM
R
EGISTERS
A
DDRESS
R
EGISTER
N
AME
B
IT
-7 B
IT
-6 B
IT
-5 B
IT
-4 B
IT
-3 B
IT
-2 B
IT
-1 B
IT
-0
0X03 CUSTOM
0 0 0 0 0 0
MaxPkt-
Size
WIDE_
En
0x04 LOW_LATENCY 0 0 0 0 0 0 0 EN
0x06 CUSTOM_INT_PACKET 0 GPIO5 GPIO4 GPIO3 GPIO0 0 GPIO2 GPIO1
XR21V1410
24
1-CH FULL-SPEED USB UART
REV. 1.4.0
3.4.3 CUSTOM_INT_PACKET (Read/Write)
This register is used to enable / disable GPIO status in the high data byte of the custom interrupt packet. See
Table 16, “Interrupt Packet Format,” on page 25 and Table 18, “Data Field of Customized Interrupt
Packet - Exar Vendor Specific,” on page 26.
CUSTOM_INT_PACKET[0]: GPIO1
•
Logic 0 = Disable GPIO1 status in custom interrupt packet.
•
Logic 1 = Enable GPIO1 status in custom interrupt packet.
CUSTOM_INT_PACKET[1]: GPIO2
•
Logic 0 = Disable GPIO2 status in custom interrupt packet.
•
Logic 1 = Enable GPIO2 status in custom interrupt packet.
CUSTOM_INT_PACKET[2]: Reserved
•
This bit is reserved and should remain ’0’.
CUSTOM_INT_PACKET[3]: GPIO0
•
Logic 0 = Disable GPIO0 status in custom interrupt packet.
•
Logic 1 = Enable GPIO0 status in custom interrupt packet.
CUSTOM_INT_PACKET[4]: GPIO3
•
Logic 0 = Disable GPIO3 status in custom interrupt packet.
•
Logic 1 = Enable GPIO3 status in custom interrupt packet.
CUSTOM_INT_PACKET[5]: GPIO4
•
Logic 0 = Disable GPIO4 status in custom interrupt packet.
•
Logic 1 = Enable GPIO4 status in custom interrupt packet.
CUSTOM_INT_PACKET[6]: GPIO5
•
Logic 0 = Disable GPIO5 status in custom interrupt packet.
•
Logic 1 = Enable GPIO5 status in custom interrupt packet.
CUSTOM_INT_PACKET[7]: Reserved
This bit is reserved and should remain ’0’.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

XR21V1410IL16-F

Mfr. #:
Buy XR21V1410IL16-F
Manufacturer:
MaxLinear
Description:
USB Interface IC 1-Ch 12Mbps 48MHz Internal clock; UART
Lifecycle:
New from this manufacturer.
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