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XR21V1410IL16-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
XR21V1410
7
REV. 1.4.0
1-CH FULL-SPEED USB UART
1.3.1.3 Device Attributes
The Device Attributes value replaces the bmAttributes field in the USB Standard Configuration Descriptor. The
default setting in the V1410 device is 0xA0. The bit field definitions are:
•
Bit 7 is reserved - set to ’1’
•
Bit 6 is Self-powered mode - set to ’0’ for bus-powered, set to ’1’ for self-powered
•
Bit 5 is Remote Wakeup support - set to ’0’ for no support, set to ’1’ for remote wakeup support
•
Bit 4:0 are reserved - set to ’0’
1.3.1.4 Device Maximum Power
The Device Maximum Power value replaces the bMaxPower field in the USB Standard Configuration
Descriptor. The value specified is in units of 2 mA. For example, the value 0x2F is decimal 47 or 94 mA. Note
that the default bMaxPower of the V1410 device is 94 mA.
1.4 UART Manager
The UART Manager enables/disables the UART including the TX and RX FIFOs. The UART Manager is
located in a separate register block from the UART registers.
1.5 UART
The UART can be configured via USB control transfers from the USB host. The UART transmitter and receiver
sections are described seperately in the following sections. At power-up, the V1410 will default to 9600 bps, 8
data bits, no parity bit, 1 stop bit, and no flow control. If a standard CDC driver accesses the V1410, defaults
will change. See ”Section 1.2, USB Device Driver” on page 5.
1.5.1 Transmitter
The transmitter consists of a 128-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet
has been received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO
of the specified UART channel. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has
completed sending the previous data byte. The TSR shifts the data out onto the TX output pin at the data rate
defined by the CLOCK_DIVISOR and TX_CLOCK_MASK registers. The transmitter sends the start bit
followed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds the stop-
bit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without parity.
If 9 bit data is selected without wide mode, the 9th bit will always be ’0’.
1.5.1.1 Wide Mode Transmit
When both 9 bit data and wide mode are enabled, two bytes of data must be written. The first byte that is
loaded into the TX FIFO are the first 8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte that is
loaded into the TX FIFO is bit-8 of the 9-bit data. The data that is transmitted on the TX pin is as follows: start
bit, 9-bit data, stop bit. Use the WIDE_MODE register to enable wide mode.
1.5.2 Receiver
The receiver consists of a 384-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the
RSR via the RX pin is transferred into the RX FIFO. Data from the RX FIFO is sent to the USB host in
response to a bulk-in request. Depending on the mode, error / status information for that data character may
or may not be stored in the RX FIFO with the data.
1.5.2.1 Normal receive operation with 7 or 8-bit data
Data that is received is stored in the RX FIFO. Any parity, framing or overrun error or break status information
related to the data is discarded. Receive data format is shown in Figure 3.
1.5.2.2 Normal receive operation with 9-bit data
The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun
error or break status information related to the data is discarded.
XR21V1410
8
1-CH FULL-SPEED USB UART
REV. 1.4.0
F
IGURE
3. N
ORMAL
O
PERATION
R
ECEIVE
D
ATA
F
ORMAT
1.5.2.3 Wide mode receive operation with 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received
data. The second byte consists of the error bits and break status. Wide mode receive data format is shown in
Figure 4.
1.5.2.4 Wide mode receive operation with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of
the received data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received /
checked. The remainder of the 2nd byte consists of the framing and overrun error bits and break status.
F
IGURE
4. W
IDE
M
ODE
R
ECEIVE
D
ATA
F
ORMAT
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags
are historical flags indicating that an error has occurred since the previous request. Therefore, no conclusion
can be drawn as to which specific byte(s) may have contained an actual error in this manner.
1.5.3 Rx FIFO Low Latency
In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to
minimize host processing. When there are 64 bytes of data in the RX FIFO, the V1410 will acknowledge a
bulk-in request from the host and transfer the data packet. If there is less than 64 bytes in the RX FIFO, the
V1410 may NAK the bulk-in request indicating that data is not ready to transfer at that time. However, if there
is less than 64 bytes in the RX FIFO and no data has been received for more than 3 character times, the
V1410 will acknowledge the bulk-in request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this increases latency unacceptably. The V1410 has a
low latency register bit that will cause the V1410 to immediately transfer any received data in the RX FIFO to
1
ST
byte
7, 8, or 9 bit data
7 6 5 4 3 2 1 0
7 = ‘0’ in 7 bit mode
1st byte
2nd byte
9 bit mode
7 6 5 4 3 2 1 0
x x x x O F B P
1st byte
B = Break
F = Framing Error
O = Overrun Error
2nd byte
7 or 8 bit mode
P = Parity Error (= ‘0’ if not enabled)
7 = ‘0’ in 7 bit mode
x = ‘0’
7 6 5 4 3 2 1 0
x x x x O F B 8 B = Break
F = Framing Error
O = Overrun Error
x = ‘0’
XR21V1410
9
REV. 1.4.0
1-CH FULL-SPEED USB UART
the USB host, i.e. it will not wait for 3 character times. The custom driver can automatically set the
RX_FIFO_LOW_LATENCY register bit to force the V1410 to be in the low latency mode, or the user may
manually set this bit. With the CDC-ACM driver, the low latency mode is automatically set whenever the baud
rate is set to a value of less than 46921 bps using the CDC_ACM_IF_SET_LINE_CODING command.
1.5.4 GPIO
The UART has 6 GPIOs. By hardware default the GPIOs are configured as inputs but may be modified by a
custom driver. Additionally, there are several modes that can be enabled to add additional feature such as
auto RTS/CTS flow control, auto DTR/DSR flow control or auto RS-485 half duplex control. See Table 14.
1.5.5 Automatic RTS/CTS Hardware Flow Control
GPIO5 and GPIO4 of the UART channel can be enabled as the RTS# and CTS# signals for Auto RTS/CTS
flow control when GPIO_MODE[2:0] = ’001’ and FLOW_CONTROL[2:0] = ’001’. Automatic RTS flow control is
used to prevent data overrun errors in local RX FIFO by de-asserting the RTS signal to the remote UART.
When there is room in the RX FIFO, the RTS pin will be re-asserted. Automatic CTS flow control is used to
prevent data overrun to the remote RX FIFO. The CTS# input is monitored to suspend/restart the local
transmitter (see Figure 5):
1.5.6 Automatic DTR/DSR Hardware Flow Control
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control
described above except that it uses the DTR# and DSR# signals. For Auto hardware flow control,
FLOW_CONTROL[2:0] = ’001’. GPIO3 and GPIO2 become DTR# and DSR#, respectively, when
GPIO_MODE[2:0] = ’010’.
F
IGURE
5. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
T ra ns m itte r
A uto C T S
M o nitor
R e c e iv e r F IF O
T rigg er R e a c he d
A uto R T S
T rigg e r Le ve l
R e m ote U A R T
U A R TB
R T S A #
C T S B #
T X B
R X A
O N O N
O F F
O N O N
O F F
1
2
3
4
1 ) C O M p o rt o p e ne d , R X F IF O em p ty , R T S A # o u tpu t is a ss e rted
2 ) S ig na l p rop ag a te d to C T S B # inp u t
3 ) D a ta by tes e n ter T X F IF O , b eg in tra n sm ittin g o n T X B
4 ) D a ta prop ag a te s to R e c eiv in g d ev ice R X A
5 ) R X F IF O re a ch e s th re sh o ld
6 ) R T S A # de -a sse rts
7 ) S ig na l p rop ag a te s to C T S B # inp u t
8 ) T ra ns m is s io n sto ps on T X B
9 ) U S B B u lk-In em p tie s R X F IF O be lo w th re sh o ld , R T S A # is a ss e rte d
1 0 ) S ig n a l p ro pa g ate d to C T S B # in p ut
1 1 ) D ata b y te s re s um e tra ns m itting o n T X B
5
6
7
8
9
10
11
R T S A # C T S B #
T X BR X A
C T S A #
T X A
R T S B #
R X B
R ec e iv e r F IF O
T rig ge r R e a ch ed
A u to R T S
T rigg er Le ve l
T ran sm itte r
A u to C T S
M o n ito r
Lo c al U A R T
U A R T A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

XR21V1410IL16-F

Mfr. #:
Buy XR21V1410IL16-F
Manufacturer:
MaxLinear
Description:
USB Interface IC 1-Ch 12Mbps 48MHz Internal clock; UART
Lifecycle:
New from this manufacturer.
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