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XR21V1410IL16-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
XR21V1410
19
REV. 1.4.0
1-CH FULL-SPEED USB UART
3.3.5 CHARACTER_FORMAT Register Description (Read/Write)
This register controls the character format such as the word length (7, 8 or 9), parity (odd, even, forced ’0’, or
forced ’1’) and number of stop bits (1 or 2).
CHARACTER_FORMAT[3:0]: Data Bits.
All other values for CHARACTER_FORMAT[3:0] are reserved.
CHARACTER_FORMAT[6:4]: Parity Mode Select
These bits select the parity mode. If 9-bit data mode has been selected, then writing to these bits will not have
any effect. In other words, there will not be an additional parity bit.
CHARACTER_FORMAT[7]: Stop Bit select
This register selects the number of stop bits to add to the transmitted character and how many stop bits to
check for in the received character.
3.3.6 FLOW_CONTROL Register Description (Read/Write)
These registers select the flow control mode. These registers should only be written to when the UART is
disabled. Writing to the FLOW_CONTROL register when the UART is enabled will result in undefined
behavior. Note that the FLOW_CONTROL register settings are used in conjunction with the GPIO_MODE
register.
T
ABLE
10: D
ATA
B
ITS
D
ATA
B
ITS
CHARACTER_FORMAT[3:0]
7 0111
8 1000
9 1001
T
ABLE
11: P
ARITY
S
ELECTION
B
IT
-6 B
IT
-5 B
IT
-4 P
ARITY SELECTION
0 0 0 No parity
0 0 1 Odd parity
0 1 0 Even parity
0 1 1 Force parity to mark, “1”
1 0 0 Force parity to space, “0”
T
ABLE
12: S
TOP
B
IT
S
ELECTION
B
IT
-7 N
UMBER OF
S
TOP
B
ITS
0 1 stop bit
2 2 stop bits
XR21V1410
20
1-CH FULL-SPEED USB UART
REV. 1.4.0
FLOW_CONTROL[2:0]: Flow control mode select
FLOW_CONTROL[3]: Half-Duplex Mode
•
Logic 0 = Normal (full-duplex) mode. The UART can transmit and receive data at the same time.
•
Logic 1 = Half-duplex Mode. In half-duplex mode, any data on the RX pin is ignored when the UART is
transmitting data.
FLOW_CONTROL[7:4]: Reserved
These bits are reserved and should remain ’0’.
3.3.7 XON_CHAR, XOFF_CHAR Register Descriptions (Read/Write)
The XON_CHAR and XOFF_CHAR registers store the XON and XOFF characters, respectively, that are used
in the Automatic Software Flow control. If the V1410 is configured in multidrop mode, the XON_CHAR and
XOFF_CHAR registers are instead used for address matching.
XON_CHAR[7:0]: XON Character
In Automatic Software Flow control mode, the UART will resume data transmission when the XON character
has been received.
For behavior in the Address Match mode, see “Section 1.5.9, Multidrop Mode with address matching” on
page 10.
XOFF_CHAR[7:0]: XOFF Character
In Automatic Software Flow control mode, the UART will suspend data transmission when the XOFF character
has been received.
For behavior in the Address Match mode, see “Section 1.5.9, Multidrop Mode with address matching” on
page 10.
3.3.8 LOOPBACK_CTL Register Descriptions (Read/Write)
LOOPBACK_CTL[1:0]: Reserved
These bits are reserved and should remain ’0’.
LOOPBACK_CTL[2]: Enable
•
Logic 0 = Internal UART (TX to RX) loopback is disabled.
•
Logic 1 = Internal UART (TX to RX) loopback is enabled.
LOOPBACK_CTL[7:3]: Reserved
These bits are reserved and should remain ’0’.
T
ABLE
13: F
LOW
C
ONTROL
M
ODE
S
ELECTION
M
ODE
B
IT
-2 B
IT
-1 B
IT
-0 M
ODE
D
ESCRIPTION
0 0 0 0 No flow control, no address matching.
1 0 0 1 HW flow control enabled. Auto RTS/CTS or DTR/DSR must be selected by
GPIO_MODE.
2 0 1 0 SW flow control enabled
3 0 1 1 Multidrop mode - RX only after address match, TX independent. (Typically
used with GPIO_MODE 3)
4 1 0 0 Multidrop mode - RX / TX only after address match. (Typically used with
GPIO_MODE 4)
XR21V1410
21
REV. 1.4.0
1-CH FULL-SPEED USB UART
3.3.9 ERROR_STATUS Register Description - Read-only
This register reports any errors that may have occurred on the line such as framing, parity and overrun as well
as break status.
ERROR_STATUS[2:0]: Reserved
These bits are reserved. Any values read from these bits should be ignored.
ERROR_STATUS[3]: Break status
•
Logic 0 = No break condition
•
Logic 1 = A break condition has been detected (clears after read).
ERROR_STATUS[4]: Framing Error
•
Logic 0 = No framing error
•
Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not
present when it is expected.
ERROR_STATUS[5]: Parity Error
•
Logic 0 = No parity error
•
Logic 1 = A parity error has been detected (clears after read).
ERROR_STATUS[6]: Overrun Error
•
Logic 0 = No overrun error
•
Logic 1 = An overrun error has been detected (clears after read). An overrun error occurs when the RX FIFO
is full and another byte of data is received.
ERROR_STATUS[7]: Break Status
•
Logic 0 = Break condition is no longer present.
•
Logic 1 = Break condition is currently being detected.
3.3.10 TX_BREAK Register Description (Read/Write)
Writing a non-zero value to this register causes a break condition to be generated continuously until the
register is cleared. If data is being shifted out of the TX pin, the data will be completely shifted out before the
break condition is generated.
3.3.11 RS485_DELAY Register Description (Read/Write)
RS485_DELAY[3:0]: Turn-around delay
This is the number of bit times the V1410 waits before de-asserting the GPIO5/RTS#/RS485 pin when it is
configured for automatic RS-485 half-duplex control.
RS485_DELAY[7:4]: Reserved
These bits are reserved and should be ’0’.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

XR21V1410IL16-F

Mfr. #:
Buy XR21V1410IL16-F
Manufacturer:
MaxLinear
Description:
USB Interface IC 1-Ch 12Mbps 48MHz Internal clock; UART
Lifecycle:
New from this manufacturer.
Delivery:
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