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AD9944KCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD9943/AD9944 Data Sheet
CCD MODE TIMING
Figure 14. CCD Mode Timing
Figure 15. Typical CCD Mode Line Clamp Timing
N
N + 1
N + 2 N + 9 N + 10
t
OD
t
S1
t
ID
t
ID
N – 10 N –
9
N
–
8 N – 1 N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2.
CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SHP
SHD
DATACLK
OUTPUT
DATA
CCD
SIGNAL
t
S2
t
CP
02905-B-015
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
DUMMY PIXELS EFFECTIVE PIXELS
PBLK
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA
02905-B-016
Rev. C | Page 16 of 20
Data Sheet AD9943/AD9944
APPLICATIONS INFORMATION
The AD9943/AD9944 are complete analog front end (AFE)
products for digital still camera and camcorder applications. As
shown in Figure 12, the CCD image (pixel) data is buffered and
sent to the AD9943/AD9944 analog input through a series
input capacitor. The AD9943/AD9944 perform the dc
restoration, CDS, gain adjustment, black level correction, and
analog-to-digital conversion. The AD9943/AD9944’s digital
output data is then processed by the image processing ASIC.
The internal registers of the AD9943/AD9944—used to control
gain, offset level, and other functions—are programmed by the
ASIC or microprocessor through a 3-wire serial digital
interface. A system timing generator provides the clock signals
for both the CCD and the AFE.
Figure 16. System Applications Diagram
Figure 17. AD9943 Recommended Circuit Configuration for CCD Mode
CCD
CCDIN
BUFFER
V
OUT
AD9943/AD9944
ADC
OUT
REGISTER
DATA
SERIAL
INTERFACE
DIGITAL
OUTPUTS
DIGITAL IMAGE
PROCESSING
ASIC
TIMING
GENERATOR
V-DRIVE
CCD
TIMING
CDS/CLAMP
TIMING
0.1
µ
F
02905-B-017
24 REFB
23 REFT
22 CCDIN
21 AVSS
D0 1
D1 2
D2 3
NC
20 AVDD
19 SHD
18 SHP
17 CLPOB
D3 4
D4 5
D5 6
D6 7
D7 8
DATA
OUTPUTS
10
D8
D9
9 10
3V
DRIVER
SUPPLY
3V
ANALOG
SUPPLY
3V
ANALOG
SUPPLY
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
12 13 14 15 16
5
CLOCK
INPUTS
3
SERIAL
INTERFACE
CCDIN
1.0µF
1.0µF
0.1µF
0.1µF
0.1µF
0.1µF
NC = NO CONNECT
32 31 30 29 28 27 26 25
NC
NC
NC
NC
SCK
SDTA
SL
11
02905-018
AD9943
TOP VIEW
(Not to Scale)
Rev. C | Page 17 of 20
AD9943/AD9944 Data Sheet
Figure 18. AD9944 Recommended Circuit Configuration for CCD Mode
INTERNAL POWER-ON RESET CIRCUITRY
After power-on, the AD9943/AD9944 automatically reset all
internal registers and perform internal calibration procedures.
This takes approximately 1 ms to complete. During this time,
normal clock signals and serial write operations may occur.
However, serial register writes are ignored until the internal
reset operation is completed.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 17 and Figure 18, a single ground plane is
recommended for the AD9943/AD9944. This ground plane
should be as continuous as possible. This ensures that all analog
decoupling capacitors provide the lowest possible impedance
path between the power and bypass pins and their respective
ground pins. All decoupling capacitors should be located as
close as possible to the package pins. A single clean power
supply is recommended for the AD9943 and AD9944, but a
separate digital driver supply may be used for DRVDD (Pin 11).
DRVDD should always be decoupled to DRVSS (Pin 12), which
should be connected to the analog ground plane. Advantages of
using a separate digital driver supply include using a lower
voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing
digital power dissipation and potential noise coupling. If the
digital outputs must drive a load larger than 20 pF, buffering
is the recommended method to reduce digital code transition
noise. Alternatively, placing series resistors close to the digital
output pins may also help reduce noise.
Note: The exposed pad on the bottom of the AD9943/AD9944
should be soldered to the GND plane of the printed circuit board.
24 REFB
23 REFT
22 CCDIN
21 AVSS
D2 1
D3 2
D0
D1
D4 3
20 AVDD
19 SHD
18 SHP
17 CLPOB
D5 4
D6 5
D7 6
D8 7
D9 8
DATA
OUTPUTS
12
D10
D11
9 10
3V
DRIVER
SUPPLY
3V
ANALOG
SUPPLY
3V
ANALOG
SUPPLY
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
12 13 14 15 16
5
CLOCK
INPUTS
3
SERIAL
INTERFACE
CCDIN
1.0µF
1.0µF
0.1µF
0.1µF
0.1µF
0.1µF
NC = NO CONNECT
32 31 30 29 28 27 26 25
NC
NC
NC
SCK
SDTA
SL
11
02905-019
AD9944
TOP VIEW
(Not to Scale)
Rev. C | Page 18 of 20
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AD9944KCPZRL

Mfr. #:
Buy AD9944KCPZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit 25 MHz CCD Signal Processor
Lifecycle:
New from this manufacturer.
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