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AD9944KCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Data Sheet AD9943/AD9944
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. AD9943 Pin Configuration
Table 6. AD9943 Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 to 10 D0 to D9 DO Digital Data Outputs.
11 DRVDD P Digital Output Driver Supply.
12 DRVSS P Digital Output Driver Ground.
13 DVDD P Digital Supply.
14 DATACLK DI Digital Data Output Latch Clock.
15 DVSS P Digital Supply Ground.
16 PBLK DI Preblanking Clock Input.
17 CLPOB DI Black Level Clamp Clock Input.
18 SHP DI CDS Sampling Clock for CCD Reference Level.
19 SHD DI CDS Sampling Clock for CCD Data Level.
20
AVDD
P
Analog Supply.
21 AVSS P Analog Ground.
22 CCDIN AI Analog Input for CCD Signal.
23 REFT AO A/D Converter Top Reference Voltage Decoupling.
24 REFB AO A/D Converter Bottom Reference Voltage Decoupling.
25 SL DI Serial Digital Interface Load Pulse.
26 SDATA DI Serial Digital Interface Data Input.
27 SCK DI Serial Digital Interface Clock Input.
28 to 30 NC NC Internally pulled down. Float or connect to GND.
31 to 32 NC NC Internally not connected.
EPAD Exposed Pad. Solder the exposed pad to the ground plane of the PCB.
1
Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
REFB
REFT
CCDIN
AVSS
D0
D1
D2
NC
2
AVDD
SHD
SHP
CLPOB
D8
D9
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
D3
D4
D5
D6
D7
NC
2
NC
1
NC
1
NC
1
SCK
SDATA
SL
1
NC = NO CONNECT. INTERNALLY PULLED DOWN. FLOAT OR CONNECT TO GND.
2
NC = NO CONNECT. INTERNALLY NOT CONNECTED.
NOTES
1. SOLDER THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB.
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD9943
TOP VIEW
(Not to Scale)
02905-003
Rev. C | Page 7 of 20
AD9943/AD9944 Data Sheet
Figure 3. AD9944 Pin Configuration
Table 7. AD9944 Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 to 10 D2 to D11 DO Digital Data Outputs.
11 DRVDD P Digital Output Driver Supply.
12 DRVSS P Digital Output Driver Ground.
13 DVDD P Digital Supply.
14
DATACLK
DI
Digital Data Output Latch Clock.
15 DVSS P Digital Supply Ground.
16 PBLK DI Preblanking Clock Input.
17 CLPOB DI Black Level Clamp Clock Input.
18 SHP DI CDS Sampling Clock for CCD Reference Level.
19
SHD
DI
CDS Sampling Clock for CCD Data Level.
20 AVDD P Analog Supply.
21 AVSS P Analog Ground.
22 CCDIN AI Analog Input for CCD Signal.
23 REFT AO A/D Converter Top Reference Voltage Decoupling.
24 REFB AO A/D Converter Bottom Reference Voltage Decoupling.
25
SL
DI
Serial Digital Interface Load Pulse.
26 SDATA DI Serial Digital Interface Data Input.
27 SCK DI Serial Digital Interface Clock Input.
28 to 30 NC NC Internally pulled down. Float or connect to GND.
31 D0 DO Digital Data Output.
32 D1 DO Digital Data Output.
EPAD Exposed Pad. Solder the exposed pad to the ground plane of the PCB.
1
Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
REFB
REFT
CCDIN
AVSS
D2
D3
D4
D1
AVDD
SHD
SHP
CLPOB
D10
D11
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
D5
D6
D7
D8
D9
D0
NC
NC
NC
SCK
SDATA
SL
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD9944
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT. INTERNALLY PULLED DOWN. FLOAT OR CONNECT TO GND.
2. SOLDER THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB.
02905-004
Rev. C | Page 8 of 20
Data Sheet AD9943/AD9944
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore
every code must have a finite width. No missing codes
guaranteed to 10-bit resolution indicates that all 1024 codes,
respectively, must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full-signal chain specification, refers to the
peak deviation of the output of the AD9943/AD9944 from a
true straight line. The point used as zero scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
( )
codesScaleFullADC
N
2LSB1 =
where N is the bit resolution of the ADC. For example, 1 LSB of
the AD9943 is 1.95 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9943/AD9944’s power supply. The PSR specification is
calculated from the change in the data outputs for a given
step change in the supply voltage.
Internal Delay for SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from the time a sampling edge is applied to the
AD9943/AD9944 until the actual sample of the input signal is
held. Both SHP and SHD sample the input signal during the
transition from low to high, so the internal delay is measured
from each clock’s rising edge to the instant the actual internal
sample is taken.
Rev. C | Page 9 of 20
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AD9944KCPZRL

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Manufacturer:
Analog Devices Inc.
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Analog Front End - AFE 12-Bit 25 MHz CCD Signal Processor
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