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AD9944KCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD9943/AD9944 Data Sheet
Parameter Min Typ Max Unit Conditions
A/D CONVERTER
Resolution 10 Bits
Differential Nonlinearity (DNL) ±0.3 LSB
No Missing Codes Guaranteed
Data Output Coding
Straight binary
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications include entire signal chain.
Gain Range
Low Gain (VGA Code = 0) 5.3 dB
Maximum Gain (VGA Code = 1023) 40 41.5 dB
Gain Accuracy ±1 dB
Peak Nonlinearity 500 mV Input Signal 0.1 % 12 dB gain applied.
Total Output Noise 0.3 LSB rms AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
1
Input signal characteristics defined as follows:
AD9944 SYSTEM SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = DVDD = DRVDD = 3 V, f
SAMP
= 25 MHz, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Conditions
CDS
Maximum Input Range before Saturation
1
1.0 V p-p
Allowable CCD Reset Transient
1
500 mV See input waveform in footnote.
Maximum CCD Black Pixel Amplitude
1
100
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Minimum Gain 5.3 dB See Figure 13 for VGA gain curve.
Maximum Gain 40 41.5 dB
See Variable Gain Amplifier section for VGA
gain equation.
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC output.
Minimum Clamp Level
0
LSB
Maximum Clamp Level 255 LSB
A/D CONVERTER
Resolution
12
Bits
Differential Nonlinearity (DNL) ±0.4 LSB
No Missing Codes Guaranteed
Data Output Coding Straight binary
Full-Scale Input Voltage 2.0 V
100mV TYP
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V TYP
INPUT SIGNAL RANGE
02905-B-002
Rev. C | Page 4 of 20
Data Sheet AD9943/AD9944
Parameter Min Typ Max Unit Conditions
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications include entire signal chain.
Gain Range
Low Gain (VGA Code = 0) 5.3 dB
Maximum Gain (VGA Code = 1023) 40 41.5 dB
Gain Accuracy
±1
dB
Peak Nonlinearity 500 mV Input Signal 0.1 % 12 dB gain applied.
Total Output Noise 0.9 LSB rms AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
1
Input signal characteristics defined as follows:
TIMING SPECIFICATIONS
C
L
= 20 pF, f
SAMP
= 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11.
Table 4.
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
CONV
40 ns
DATACLK High/Low Pulse Width t
ADC
16 20 ns
SHP Pulse Width t
SHP
10 ns
SHD Pulse Width t
SHD
10 ns
CLPOB Pulse Width
1
t
COB
2 20 Pixels
SHP Rising Edge to SHD Falling Edge t
S1
10 ns
SHP Rising Edge to SHD Rising Edge t
S2
16 20 ns
Internal Clock Delay
t
ID
3.0
ns
DATA OUTPUTS
Output Delay t
OD
9.5 ns
Pipeline Delay
9
Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time
t
LS
10
ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
1
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
100mV TYP
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V TYP
INPUT SIGNAL RANGE
02905-B-002
Rev. C | Page 5 of 20
AD9943/AD9944 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter (With Respect To) Min Max Unit
AVDD (AVSS) −0.3 +3.9 V
DVDD (DVSS) −0.3 +3.9 V
DRVDD (DRVSS) −0.3 +3.9 V
Digital Outputs (DRVSS) −0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK (DVSS) −0.3 DVDD + 0.3 V
CLPOB, PBLK (DVSS) −0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS (AVSS) −0.3 DVDD + 0.3 V
REFT, REFB, CCDIN
−0.3
AVDD + 0.3
V
Junction Temperature 150 °C
Lead Temperature (10 sec) 300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The thermal resistance of a 32-lead LFCSP package
(with the exposed bottom pad soldered to the board GND)
is θ
JA
= 27.7°C / W.
ESD CAUTION
Rev. C | Page 6 of 20
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD9944KCPZRL

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Buy AD9944KCPZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit 25 MHz CCD Signal Processor
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New from this manufacturer.
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