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79RC32V332-133DHGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
13 of 30 May 4, 2004
IDT 79RC32332
pci_host_mode Settings
During cold reset initialization, the RC32332’s PCI interface can be set to the Satellite or Host mode settings. When set to the Host mode, the CPU
must configure the RC32332’s PCI configuration registers, including the read-only registers. If the RC32332’s PCI is in the PCI-boot mode Satellite
mode, read-only configuration registers are loaded by the serial EEPROM.
Clock Parameters — RC32332
Ta Commercial = 0°C to +70°C; Ta Industrial = -40°C to +85°C
3.3V version
: V
cc
Core = +3.3V±5%; V
cc
I/O = +3.3V±5%
2.5V version
: V
cc
Core = +2.5V±5%; V
cc
I/O = +3.3V±5%
Pin Reset Boot Mode Description Value Mode Settings
mem_addr[20] PCI host mode PCI is in satellite mode 1 PCI_satellite
PCI is in host mode (typical system) 0 PCI_host
Table 4 RC32332 pci_host_mode Initialization Settings
Parameter Symbol Test Conditions
RC32332
100MHz
RC32332
133MHz
RC32332
150MHz
Units
Min Max Min Max Min Max
cpu_masterclock HIGH t
MCHIGH
Transition ≤ 2ns 8 — 6.75 — 6 — ns
cpu_masterclock LOW t
MCLOW
Transition ≤ 2ns 8 — 6.75 — 6 — ns
cpu_masterclock period
1
- 3.3V ver.
1.
cpu_masterclock frequency should never be below pci_clk frequency if PCI interface is used.
t
MCP
— 20 66.6 15 66.6 13.33 66.6 ns
cpu_masterclock period
1
- 2.5V ver. t
MCP
— 20 40.0 15 40.0 13.33 40.0 ns
cpu_masterclock Rise & Fall Time
2
2.
Rise and Fall times are measured between 10% and 90%.
t
MCRise,
t
MCFall
— —3—3—3ns
cpu_masterclock Jitter t
JITTER
——+ 250 — + 250 — + 200 ps
pci_clk Rise & Fall Time t
PCRise,
t
PCFall
PCI 2.2 — 1.6 — 1.6 — 1.6 ns
pci_clk Period
1
t
PCP
20 — 20 — 20 — ns
jtag_tck Rise & Fall Time t
JCRise,
t
JCFall
— —5—5—5ns
ejtag_dck period t
DCK,
t
11
10 — 10 — 10 — ns
jtag_tck clock period t
TCK,
t
3
100 — 100 — 100 — ns
ejtag_dclk High, Low Time t
DCK High,
t
9
t
DCK Low,
t
10
4—4—4—ns
ejtag_dclk Rise, Fall Time t
DCK Rise,
t
9
t
DCK Fall,
t
10
—1—1—1ns
output_clk
3
3.
Output_clk should not be used in a system. Only the cpu_masterclock or its derivative must be used to drive all the subsystems with designs based on the RC32334/RC32332.
Refer to the RC32334/RC32332 Device Errata for more information.
t
DO
21 N/A N/A N/A N/A N/A N/A —
cpu_coldreset_n
Asserted during power-up
power-on sequence 120 — 120 — 120 — ms
cpu_coldreset_n Rise Time t
CRRise
—5—5—5ns
Table 5 Clock Parameters - RC32332
14 of 30 May 4, 2004
IDT 79RC32332
Reset Specification
Figure 3 Mode Configuration Interface Cold Reset Sequence
VCC
cpu_coldreset_n
modebit[9:0]
>= 110 ms
cpu_masterclk
>= 10 ms
(MClk)
120 ms
t
CRRise
15 of 30 May 4, 2004
IDT 79RC32332
AC Timing Characteristics — RC32332
Ta Commercial = 0°C to +70°C; Ta Industrial = -40°C to +85°C
3.3V version
: V
cc
Core = +3.3V±5%; V
cc
I/O = +3.3V±5%
2.5V version
: V
cc
Core = +2.5V±5%; V
cc
I/O = +3.3V±5%
Signal Symbol
Reference
Edge
100MHz
1
133MHz
1
150MHz
1
Units
User Manual
Timing
Diagram
Reference
Min Max Min Max Min Max
Local System Interface
mem_data[31:0] (data phase) Tsu2 cpu_masterclk rising 6 — 5 — 4.8 — ns Chapter 9, Figures
9.2 and 9.3
Chapter 10,
Figures 10.6
through 10.8
mem_data[31:0] (data phase) Thld2 cpu_masterclk rising 1.5 — 1.5 — 1.5 — ns
cpu_dt_r_n Tdo3 cpu_masterclk rising — 15 — 12 — 10 ns
mem_data[31:0] Tdo4 cpu_masterclk rising — 12 — 10 — 9.3 ns
mem_data[31:0] output hold time Tdoh1 cpu_masterclk rising 1 — 1 — 1 — ns
mem_data[31:0] (tristate disable
time)
Tdz cpu_masterclk rising — 12
2
—10
2
—9.3
2
ns
mem_data[31:0] (tristate to data
time)
Tzd cpu_masterclk rising — 12
2
—10
2
—9.3
2
ns
mem_wait_n Tsu6 cpu_masterclk rising 9 — 7 — 6 — ns
mem_wait_n Thld8 cpu_masterclk rising 1 — 1 — 1 — ns
mem_addr[22:2] Tdo5 cpu_masterclk rising — 12 — 9 — 8 ns
mem_cs_n[5:0] Tdo6 cpu_masterclk rising — 12 — 9 — 8 ns
mem_oe_n, mem_245_oe_n Tdo7 cpu_masterclk rising — 12 — 9 — 8 ns
mem_we_n[3:0] Tdo7a cpu_masterclk rising — 15 — 12 — 10 ns
mem_245_dt_r_n Tdo8 cpu_masterclk rising — 15 — 12 — 10 ns
mem_addr[25:2]
mem_cs_n[5:0]
mem_oe_n, mem_we_n[3:0],
mem_245_dt_r_n,
mem_245_oe_n
Tdoh3 cpu_masterclk rising 1.5 — 1.5 — 1.5 — ns
PCI for 3.3V Device
3
pci_ad[31:0], pci_cbe_n[3:0],
pci_par, pci_frame_n, pci_trdy_n,
pci_irdy_n, pci_stop_n, pci_perr_n,
pci_serr_n, pci_devsel_n,
pci_lock_n
Tsu pci_clk rising 3—3—3—ns
pci_idsel, pci_req_n[2],
pci_req_n[1], pci_req_n[0],
pci_gnt_n[0], pci_inta_n
Tsu pci_clk rising 5—5—5—ns
pci_gnt_n[0] Tsu pci_clk rising 5 — 5 — 5 — ns
pci_ad[31:0], pci_cbe_n[3:0],
pci_par, pci_frame_n, pci_trdy_n,
pci_irdy_n, pci_stop_n, pci_perr_n,
pci_serr_n, pci_devsel_n,
pci_lock_n
4
Thld pci_clk rising 0 — 0 — 0 — ns
Table 6 AC Timing Characteristics - RC32332 (Part 1 of 4)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

79RC32V332-133DHGI

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Processors - Application Specialized
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