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79RC32V332-133DHGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
7 of 30 May 4, 2004
IDT 79RC32332
pci_req_n[2] Input Z — PCI Bus Request #2 Negated Requires an external pull-up.
Host mode: pci_req_n[2] is an input indicating a request from an external device.
Satellite mode: used as pci_idsel pin which selects this device during a configuration read or write.
Alternate function: pci_idsel (satellite).
pci_req_n[0] I/O Z High PCI Bus Request #0 Negated Requires an external pull-up for burst mode.
Host mode: pci_req_n[0] is an input indicating a request from an external device.
Satellite mode: pci_req_n[0] is an output indicating a request from this device.
pci_gnt_n[2] Output Z
1
High PCI Bus Grant #2 Negated Recommend an external pull-up.
Host mode: pci_gnt_n[2] is an output indicating a grant to an external device.
Satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin. External pull-up is required.
Alternate function: pci_inta_n (satellite).
pci_gnt_n[1]
(can only be used as
alternate function)
I/O X for 1 pci
clock then
H
2
High PCI Bus Grant #1 Negated Recommend external pull-up.
Host mode: not used as pci_gnt_n[1]. Must be used as alternate function PIO[7].
Satellite mode: Not used as pci_gnt_n[1]. Used as pci_eprom_cs output pin for Serial Chip Select for
loading PCI Configuration Registers in the RC32332 Reset Initialization Vector PCI boot mode. Defaults
to the output direction at reset time.
1st Alternate function: pci_eeprom_cs (satellite).
2nd Alternate function: PIO[7].
pci_gnt_n[0] I/O Z High PCI Bus Grant #0 Negated
Host mode: pci_gnt_n[0] is an output indicating a grant to an external device. Recommend external pull-
up.
Satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. Requires external pull-up.
pci_inta_n Output
Open-
collec-
tor
ZPCIPCI Interrupt #A Negated
Uses pci_gnt_n[2]. See the PCI subsection.
pci_lock_n Input — PCI Lock Negated
Driven by the Bus Master to indicate that an exclusive operation is occurring.
1
Z in host mode; L in satellite non-boot mode; Z in satellite boot mode.
2
H in host mode, L in satellite non-boot and boot modes. X = unknown.
SDRAM Control Interface
sdram_addr_12 Output L High SDRAM Address Bit 12 and Precharge All
SDRAM mode: Provides SDRAM address bit 12 (10 on the SDRAM chip) during row address and "pre-
charge all" signal during refresh, read and write command.
sdram_ras_n Output H High SDRAM RAS Negated
SDRAM mode: Provides SDRAM RAS control signal to all SDRAM banks.
sdram_cas_n Output H High SDRAM CAS Negated
SDRAM mode: Provides SDRAM CAS control signal to all SDRAM banks.
sdram_we_n Output H High SDRAM WE Negated
SDRAM mode: Provides SDRAM WE control signal to all SDRAM banks.
sdram_cke Output H High SDRAM Clock Enable
SDRAM mode: Provides clock enable to all SDRAM banks.
sdram_cs_n[3:0] Output H High SDRAM Chip Select Negated Bus Recommend an external pull-up.
SDRAM mode: Provides chip select to each SDRAM bank.
SODIMM mode: Provides upper select byte enables [7:4].
sdram_s_n[1:0] Output H High SDRAM SODIMM Select Negated Bus
SDRAM mode: Not used.
SDRAM SODIMM mode: Upper and lower chip selects.
Name Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 3 of 6)
8 of 30 May 4, 2004
IDT 79RC32332
sdram_bemask_n
[3:0]
Output H High SDRAM Byte Enable Mask Negated Bus (DQM)
SDRAM mode: Provides byte enables for each byte lane of all DRAM banks.
SODIMM mode: Provides lower select byte enables [3:0].
sdram_245_oe_n Output H Low SDRAM FCT245 Output Enable Negated Recommend an external pull-up.
SDRAM mode: Controls output enable to optional FCT245 transceiver bank by asserting during both
reads and writes to any DRAM bank.
sdram_245_dt_r_n Output Z High SDRAM FCT245 Direction Transmit/Receive Recommend an external pull-up.
Uses cpu_dt_r_n. See CPU Core Specific Signals below.
On-Chip Peripherals
dma_ready_n[0] I/O Z Low DMA Ready Negated Bus Requires an external pull-up.
Ready mode: Input pin for general purpose DMA channel 0 that can initiate the next datum in the current
DMA descriptor frame.
Done mode: Input pin for general purpose DMA channel 0 that can terminate the current DMA descriptor
frame.
dma_ready_n[0] 1st Alternate function PIO[0]; 2nd Alternate function: dma_done_n[0].
pio[7:0] I/O See
related
pins
Low Programmable Input/Output
General purpose pins that can each can be configured as a general purpose input or general purpose
output. These pins are multiplexed with other pin functions:
pci_gnt_n[1] (pci_eeprom_cs), spi_mosi, spi_sck, spi_ss_n, spi_miso, uart_rx[0], uart_tx[0],
dma_ready_n[0]. Note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time.
The others default to inputs.
uart_rx[0] I/O Z Low UART Receive Data Bus
UART mode: UART channel receive data.
uart_rx[0] Alternate function: PIO[2].
uart_tx[0] I/O Z Low UART Transmit Data Bus Recommend an external pull-up.
UART mode: UART channel send data. Note that this pin defaults to an input at reset time and must be
programmed via the PIO interface before being used as a UART output.
uart_tx[0] Alternate function: PIO[1].
spi_mosi I/O L Low SPI Data Output
Serial mode: Output pin from RC32332 as an Input to a Serial Chip for the Serial data input stream.
In PCI satellite mode, acts as an Output pin from RC32332 that connects as an Input to a Serial Chip for
the Serial data input stream for loading PCI Configuration Registers in the RC32332 Reset Initialization
Vector PCI boot mode.
1st Alternate function: PIO[6]. Defaults to the output direction at reset time.
2nd Alternate function: pci_eeprom_mdo.
spi_miso I/O Z Low SPI Data Input
Serial mode: Input pin to RC32332 from the Output of a Serial Chip for the Serial data output stream.
In PCI satellite mode, acts as an Input pin from RC32332 that connects as an output to a Serial Chip for
the Serial data output stream for loading PCI Configuration Registers in the RC32332 Reset Initialization
Vector PCI boot mode. Defaults to input direction at reset time.
1st Alternate function: PIO[3].
2nd Alternate function: pci_eeprom_mdi.
spi_sck I/O L Low SPI Clock
Serial mode: Output pin for Serial Clock.
In PCI satellite mode, acts as an Output pin for Serial Clock for loading PCI Configuration Registers in the
RC323332 Reset Initialization Vector PCI boot mode.
1st Alternate function: PIO[5]. Defaults to the output direction at reset time.
2nd Alternate function: pci_eeprom_sk.
Name Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 4 of 6)
9 of 30 May 4, 2004
IDT 79RC32332
spi_ss_n I/O H Low SPI Chip Select
Output pin selecting the serial protocol device as opposed to the PCI satellite mode EEPROM device.
Alternate function: PIO[4]. Defaults to the output direction at reset time.
CPU Core Specific Signals
cpu_nmi_n Input — CPU Non-Maskable Interrupt Requires an external pull-up.
This interrupt input is active low to the CPU.
cpu_masterclk Input — CPU Master System Clock
Provides the basic system clock.
cpu_int_n[1:0] Input — CPU Interrupt Requires an external pull-up.
These interrupt inputs are active low to the CPU.
cpu_coldreset_n Input L — CPU Cold Reset
This active-low signal is asserted to the RC32332 after V
cc
becomes valid on the initial power-up. The
Reset initialization vectors for the RC32332 are latched by cold reset.
cpu_dt_r_n Output Z — CPU Direction Transmit/Receive
This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during
read operations.
1st Alternate function: mem_245_dt_r_n.
2nd Alternate function: sdram_245_dt_r_n.
JTAG Interface Signals
jtag_tck Input — JTAG Test Clock Requires an external pull-down.
An input test clock used to shift into or out of the Boundary-Scan register cells. jtag_tck is independent of
the system and the processor clock with nominal 50% duty cycle.
jtag_tdi,
ejtag_dint_n
Input — JTAG Test Data In Requires an external pull-up.
On the rising edge of jtag_tck, serial input data are shifted into either the Instruction or Data register,
depending on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the
debug unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG).
This pin is also used as the ejtag_dint_n signal in the EJTAG mode.
jtag_tdo,
ejtag_tpc
Output Z High JTAG Test Data Out
The jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck.
When no data is shifted out, the jtag_tdo is tri-stated. During Real Time Mode, this signal provides a non-
sequential program counter at the processor clock or at a division of processor clock. This pin is also
used as the ejtag_tpc signal in the EJTAG mode.
jtag_tms Input — JTAG Test Mode Select Requires an external pull-up.
The logic signal received at the jtag_tms input is decoded by the TAP controller to control test operation.
jtag_tms is sampled on the rising edge of the jtag_tck.
jtag_trst_n Input L — JTAG Test Reset
When neither JTAG nor EJTAG are being used, jtag_trst_n must be driven low (pulled down) or the
jtag_tms/ejtag_tms signals must be pulled up and jtag_clk actively clocked.
ejtag_dclk Output Z — EJTAG Test Clock
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the
ejtag_tpc signal at the processor clock speed or any division of the internal pipeline.
Name Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 5 of 6)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

79RC32V332-133DHGI

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Processors - Application Specialized
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