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79RC32V332-133DHGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
19 of 30 May 4, 2004
IDT 79RC32332
Standard EJTAG Timing — RC32332
Figure 4 represents the timing diagram for the EJTAG interface signals.
The standard JTAG connector is a 10-pin connector providing 5 signals and 5 ground pins. For Standard EJTAG, a 24-pin connector has been
chosen providing 12 signals and 12 ground pins. This guarantees elimination of noise problems by incorporating signal-ground type arrangement.
Refer to the RC32334/RC32332 User Reference Manual for connector pinout and mechanical specifications.
Figure 4 Standard EJTAG Timing
jtag_tdi/ejtag_dint_n
ejtag_tms, jtag_tms
jtag_tdo/ejtag_tpc,
ejtag_tpc[8:2]
jtag_tdo
jtag_tdo ejtag_tpc
ejtag_pcst[2:0]
jtag_trst_n
jtag_tck
ejtag_dclk
ejtag_pcst
t3
t14
t14
t1
t2
t15
t15
t9 t10
t5 t6
t4
t8
t7
t13
t12
t11
ejtag_tpc,ejtag_pcst[2:0] capture
Notes to diagram:
t1 = t
TCKlow
t2 = t
TCKHIGH
t3 = t
TCK
t4 = t
TDODO
t5 = t
TDIS
t6 = t
TDIH
t7 = t
PCSTDO
t8 = t
TPCDO
t9 = t
DCKHIGH
t10 = t
DCKLOW
t11 = t
DCK
t12 = t
TRSTDO
t13 = t
TRSTR
t14 = t
TCK RISE, tTCK FALL
t15 = t
DCK RISE,
t
DCK FALL
20 of 30 May 4, 2004
IDT 79RC32332
Output Loading for AC Testing
Note: PCI pins have been correlated to PCI 2.2.
Recommended Operation Temperature and Supply Voltage
3.3V Device
2.5V Device
Signal Cld
All High Drive Signals 50 pF
All Low Drive Signals 25 pF
Figure 5 Output Loading for AC Testing
Grade Ambient Temperature Gnd V
cc
IO V
cc
Core V
cc
P
Commercial 0°C to +70°C Ambient 0V 3.3V±5% 3.3V±5% 3.3V±5%
Industrial -40°C to +85°C Ambient 0V 3.3V±5% 3.3V±5% 3.3V±5%
Table 7 Temperature and Voltage — 3.3V Device
Grade Ambient Temperature Gnd V
cc
IO V
cc
Core V
cc
P
Commercial 0°C to +70°C Ambient 0V 3.3V±5% 2.5V±5% 2.5V±5%
Industrial -40°C to +85°C Ambient 0V 3.3V±5% 2.5V±5% 2.5V±5%
Table 8 Temperature and Voltage — 2.5V Device
–
+
To Device
Under Test
C
LD
V
REF
+1.5V
21 of 30 May 4, 2004
IDT 79RC32332
DC Electrical Characteristics — RC32332
Ta Commercial = 0°C to +70°C; Ta Industrial = -40°C to +85°C
3.3V version
: V
cc
Core = +3.3V±5%; V
cc
I/O = +3.3V±5%
2.5V version
: V
cc
Core = +2.5V±5%; V
cc
I/O = +3.3V±5%
Capacitive Load Deration — RC32332
Refer to the IDT document 79RC32332 IBIS Model
located on the company’s web site.
Parameter
RC32332
1
1.
At all pipeline frequencies.
Pin Numbers Conditions
Minimum Maximum
Input Pads V
IL
— 0.8V 52, 64, 95, 160, 161, 164, 166-169, 176, 191 —
V
IH
2.0V — —
LOW Drive
Output
Pads
V
OL
— 0.4V 41-45, 48, 170, 171, 174, 175, 177-180, 185-190, 195-200, 207,
208
|I
OUT
| = 6mA
V
OH
V
cc
- 0.4V — |I
OUT
| = 8mA
V
IL
—0.8V —
V
IH
2.0V — —
HIGH
Drive Out-
put Pads
V
OL
— 0.4V 1- 5, 8, 13-15, 18-25, 28-35, 38-40, 49-51, 53- 57, 60, 61, 63, 65-
67,70-76, 79, 80, 83-87, 90-94, 153, 154, 156, 158, 165, 194,
201, 204, 205, 206
|I
OUT
| = 7mA
V
OH
V
cc
- 0.4V — |I
OUT
| = 16mA
V
IL
—0.8V —
V
IH
2.0V — —
PCI Drive
Input Pads
V
IL
— — 123, 155, 157, 159 Per PCI 2.2
V
IH
——
PCI Drive
Output
Pads
V
OL
— — 96, 97, 100-109, 112-119, 122, 124-129, 132-139, 142-149, 152 Per PCI 2.2
V
OH
——
V
IL
——
V
IH
——
All Pads C
IN
— 10pF All input pads except 155 and 156 —
C
IN
2
2.
Applies only to pad 155.
5pf 12pF 155 Per PCI 2.2
C
IN
3
3.
Applies only to pad 156.
8pF 156
Per PCI 2.2
C
OUT
— 10pF All output pads —
I/O
LEAK
—10µA All non-internal pull-up pins Input/Output Leakage
I/O
LEAK
—50µA All internal pull-up pins Input/Output Leakage
Table 9 DC Electrical Characteristics - RC32332
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

79RC32V332-133DHGI

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Buy 79RC32V332-133DHGI
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IDT
Description:
Processors - Application Specialized
Lifecycle:
New from this manufacturer.
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