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79RC32V332-133DHGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
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IDT 79RC32332
Secondly, the RC32332 implements additional reporting signals
intended to simplify the task of system debugging when using a logic
analyzer. This product allows the logic analyzer to differentiate transac-
tions initiated by DMA from those initiated by the CPU and further allows
CPU transactions to be sorted into instruction fetches vs. data fetches.
Finally, the RC32332 implements a full boundary scan capability,
allowing board manufacturing diagnostics and debug.
Packaging
The RC32332 is packaged using a 208 Quad Flat Pack (QFP)
package.
Thermal Considerations
The RC32332 consumes less than 2.0 W peak power. The device is
guaranteed in an ambient temperature range of 0° to +70° C for
commercial temperature devices; -40° to +85° C for industrial tempera-
ture devices.
Revision History
November 15, 2000: Initial publication.
December 12, 2000: Changed Max values for cpu_masterclock
period in Table 5 and added footnote. In Table 1, added 2nd alternate
function for spi_mosi, spi_miso, spi_sck. In Table 11, added “2” in Alt
column for pins 186, 187, 188. In RC32332 Alternate Signal Functions
table, added pin names in Alt #2 column for pins 186, 187, 188.
January 4, 2001: In Table 6 under Interrupt Handling, changed
Tdoh9 to Thld13 and moved the values for Tsu9 from the Max to the Min
column.
February 23, 2001: In Table 1, changed alternate function for
uart_tx[0] from PIO[3] to PIO[1]. In Table 11, changed the number of
alternate pins for Pin 156 from 1 to 2. In Table 12, added PIO[7] to Alt #2
column for Pin 156 and changed PIO[3] to PIO[1] for Pin 207.
March 13, 2001: Changed upper ambient temperature for industrial
and commercial uses from +70° C to +85° C.
June 7, 2001: In the Clock Parameters table, added footnote 3 to
output_clk category and added NA to Min and Max columns. In Figure 3
(Reset Specification), enhanced signal line for cpu_masterclk. In Local
System Interface section of AC Timing Characteristics table, changed
values in Min column for last category of signals (Tdoh3) from 1.5 to 2.5
for both speeds. In SDRAM Controller section of same table, changed
values in Min column for last category of signals (9 signals) from 1 to 2.5
for both speeds.
September 14, 2001: In the Reset category of Table 6: switched
mem_addr[19:17] from Tsu22 and Thld22 to Tsu10 and Thld10;
switched mem_addr[22:20] from Tsu10 and Thld10 to Tsu22 and
Thld22; moved ejtag_pcst[2:0] from Reset to Debug Interface category
under Tsu20 and Thld20.
November 1, 2001: Added Input Voltage Undershoot parameter and
2 footnotes to Table 10. Changed to DH package.
May 2, 2002: Changed from PCI 2.1 to 2.2 compliant. Added 512 MB
SDRAM support. Changed upper ambient temperature for commercial
uses back from +85° C to +70° C (changed erroneously from 70 to 85
on March 13, 2001). Added Reset State Status column to Table 1.
Revised description of jtag_trst_n in Table 1 and changed this pin to a
pull-down instead of a pull-up.
July 3, 2002: This data sheet now describes revision Y silicon and is
no longer applicable to revision Z.
July 12, 2002: Added 150MHz speed grade. In Table 6: DMA
section, changed Thld9 Min values from 2 to 1; in PIO section, changed
Thld9 Min values from 2 to 1. Changed revision Y data sheet from
Preliminary to Final.
September 18, 2002: Added cpu_coldreset_n rise time to Table 5,
Clock Parameters. Added mem_addr[16] and sdram_addr[16] to Tables
1 and 12. Changed Logic Diagram to include sdram_addr[16].
December 18, 2002: In the Reset section of Table 6, AC Timing
Characteristics, setup and hold time categories for cpu_coldreset_n
have been deleted.
September 2, 2003: Added 2.5V version of device. Changed tables
to include 2.5V values where appropriate. Added a Power Consumption
table, Temperature and Voltage table, and Power Curves for the 2.5V
device. In the PCI category of Table 6, created separate sections for
3.3V and 2.5V devices and in 2.5V section changed time to 4 ns for
pci_cbe_n[3:0], pci_frame_n, pci_trdy_n, and pci_irdy_n. In Table 8,
added 3 new categories (Input Pads, PCI Input Pads, and All Pads) and
added footnotes 2 and 3. In Table 13, pins 181 and 184 were changed
from Vcc Core to Vcc I/O.
March 24, 2004: In Table 1, changed description in Satellite Mode
for pci_rst_n. Specified “cold” reset on pages 12 and 13. Changed
several values in Table 12, Absolute Maximum Ratings, and changed
footnote 1 to that table.
May 4, 2004: Revised values in Table 9, Power Consumption.
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IDT 79RC32332
Pin Description Table
The following table lists the pins provided on the RC32332. Note that those pin names followed by “_n” are active-low signals. All external pull-ups
and pull-downs require
10 kΩ resistor.
Name Type
Reset
State
Status
Drive
Strength
Capability
Description
Local System Interface
mem_data[31:0] I/O Z High Local system data bus
Primary data bus for memory. I/O and SDRAM.
mem_addr[22:2] I/O [22:10] Z
[9:2] L
[22:17] Low
[16:2] High
Memory Address Bus
These signals provide the Memory or DRAM address, during a Memory or DRAM bus transaction. During
each word data, the address increments either in linear or sub-block ordering, depending on the transac-
tion type. The table below indicates how the memory write enable signals are used to address discreet
memory port width types.
mem_addr[22] Alternate function: reset_boot_mode[1].
mem_addr[21] Alternate function: reset_boot_mode[0].
mem_addr[20] Alternate function: reset_pci_host_mode.
mem_addr[19] Alternate function: modebit [9].
mem_addr[18] Alternate function: modebit [8].
mem_addr[17] Alternate function: modebit [7].
mem_addr[16] Alternate function: sdram_addr[16].
mem_addr[15] Alternate function: sdram_addr[15].
mem_addr[14] Alternate function: sdram_addr[14].
mem_addr[13] Alternate function: sdram_addr[13].
mem_addr[11] Alternate function: sdram_addr[11].
mem_addr[10] Alternate function: sdram_addr[10].
mem_addr[9] Alternate function: sdram_addr[9].
mem_addr[8] Alternate function: sdram_addr[8].
mem_addr[7] Alternate function: sdram_addr[7].
mem_addr[6] Alternate function: sdram_addr[6].
mem_addr[5] Alternate function: sdram_addr[5].
mem_addr[4] Alternate function: sdram_addr[4].
mem_addr[3] Alternate function: sdram_addr[3].
mem_addr[2] Alternate function: sdram_addr[2].
mem_cs_n[5:0] Output H Low Memory Chip Select Negated Recommend an external pull-up.
Signals that a Memory Bank is actively selected.
mem_oe_n Output H High Memory Output Enable Negated Recommend an external pull-up.
Signals that a Memory Bank can output its data lines onto the cpu_ad bus.
mem_we_n[3:0] Output H High Memory Write Enable Negated Bus
Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and
mem_addr[1:0] signals for 8-bit or 16-bit wide addressing.
Table 1 Pin Descriptions (Part 1 of 6)
Port Width
Pin Signals
mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0]
DMA (32-bit) mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0]
32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0]
16-bit Byte High Write Enable mem_addr[1] Not Used (Driven
Low)
Byte Low Write
Enable
8-bit Not Used (Driven High) mem_addr[1] mem_addr[0] Byte Write Enable
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IDT 79RC32332
mem_wait_n Input — Memory Wait Negated Requires an external pull-up.
SRAM/IOI/IOM modes: Allows external wait-states to be injected during the last cycle before data is sam-
pled.
DPM (dual-port) mode: Allows dual-port busy signal to restart memory transaction.
Alternate function: sdram_wait_n.
mem_245_oe_n Output H Low Memory FCT245 Output Enable Negated
Controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to
a memory or I/O bank.
mem_245_dt_r_n Output Z High Memory FCT245 Direction Xmit/Rcv Negated Recommend an external pull-up.
Alternate function: cpu_dt_r_n. See CPU Core Specific Signals below.
output_clk Output cpu_mas
terclk
High Output Clock
Optional clock output.
PCI Interface
pci_ad[31:0] I/O Z PCI PCI Multiplexed Address/Data Bus
Address driven by Bus Master during initial frame_n assertion, and then the Data is driven by the Bus
Master during writes; or the Data is driven by the Bus Slave during reads.
pci_cbe_n[3:0] I/O Z PCI PCI Multiplexed Command/Byte Enable Bus
Command (not negated) Bus driven by the Bus Master during the initial frame_n assertion. Byte Enable
Negated Bus driven by the Bus Master during the data phase(s).
pci_par I/O Z PCI PCI Parity
Even parity of the pci_ad[31:0] bus. Driven by Bus Master during Address and Write Data phases. Driven
by the Bus Slave during the Read Data phase.
pci_frame_n I/O Z PCI PCI Frame Negated
Driven by the Bus Master. Assertion indicates the beginning of a bus transaction. De-assertion indicates
the last datum.
pci_trdy_n I/O Z PCI PCI Target Ready Negated
Driven by the Bus Slave to indicate the current datum can complete.
pci_irdy_n I/O Z PCI PCI Initiator Ready Negated
Driven by the Bus Master to indicate that the current datum can complete.
pci_stop_n I/O Z PCI PCI Stop Negated
Driven by the Bus Slave to terminate the current bus transaction.
pci_idsel_n Input — PCI Initialization Device Select
Uses pci_req_n[2] pin. See the PCI subsection.
pci_perr_n I/O Z PCI PCI Parity Error Negated
Driven by the receiving Bus Agent 2 clocks after the data is received, if a parity error occurs.
pci_serr_n I/O
Open-
collec-
tor
ZPCISystem Error Requires an external pull-up.
Driven by any agent to indicate an address parity error, data parity during a Special Cycle command, or
any other system error.
pci_clk Input — PCI Clock
Clock for PCI Bus transactions. Uses the rising edge for all timing references.
pci_rst_n Input L — PCI Reset Negated
Host mode: Resets all PCI related logic.
Satellite mode: Resets all PCI related logic and also warm resets the 32332.
pci_devsel_n I/O Z PCI PCI Device Select Negated
Driven by the target to indicate that the target has decoded the present address as a target address.
Name Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 2 of 6)
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79RC32V332-133DHGI

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