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72V841L15PFI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3 VOLT DUAL CMOS SyncFIFO™
DUAL 256 X 9, DUAL 512 X 9,
DUAL 1,024 X 9, DUAL 2,048 X 9,
DUAL 4,096 X 9 , DUAL 8,192 X 9
IDT72V801
IDT72V811
IDT72V821
IDT72V831
IDT72V841
IDT72V851
NOVEMBER 2014
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4093/5
FEATURES:
••
••
• The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs
••
••
• The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs
••
••
• The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs
••
••
• The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs
••
••
• The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs
••
••
• The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs
••
••
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
••
••
• Ideal for prioritization, bidirectional, and width expansion
applications
••
••
• 10 ns read/write cycle time
••
••
• 5V input tolerant
••
••
• Separate control lines and data lines for each FIFO
••
••
• Separate Empty, Full, programmable Almost-Empty and
Almost-Full flags for each FIFO
••
••
• Enable puts output data lines in high-impedance state
••
••
• Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/
STQFP)
••
••
• Industrial temperature range (–40
°°
°°
°C to +85
°°
°°
°C) is available
••
••
• Green parts available, see ordering information
DESCRIPTION:
The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are
dual synchronous (clocked) FIFOs. The device is functionally equivalent to
two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins.
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data
port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,
QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2).
Data is written into each of the two arrays on every rising clock edge of the Write
Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are
asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2). The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation.
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full
(PAFA, PAFB), are provided for each FIFO bank to improve memory utilization.
If not programmed, the programmable flags default to Empty+7 for PAEA and
PAEB, and Full-7 for PAFA and PAFB.
The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture
lends itself to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA1
WENA2
DA
0
- DA
8
LDA
OFFSET REGISTERINPUT REGISTER
WRITE CONTROL
LOGIC
RESET LOGIC
OUTPUT REGISTER
OEA
RSA
QA
0
- QA
8
RCLKA
RENA1
RENA2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EFA
PAEA
PAFA
FFA
4093 drw 01
WCLKB
WENB1
WENB2
DB
0
- DB
8
LDB
OFFSET REGISTERINPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
OUTPUT REGISTER
OEB
RSB
QB
0
- QB
8
RCLKB
RENB1
RENB2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EFB
PAFB
FFB
PAEB
WRITE POINTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
2
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
TM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
TQFP (PN64, order code: PF)
STQFP (PP64, order code: TF)
TOP VIEW
QA
1
QA
2
QA
3
QA
4
QA
5
QA
6
QA
7
QA
8
V
CC
WENA
2
/LDA
WCLKA
WENA
1
RSA
DA
8
DA
7
DA
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
QB0
FFB
EFB
OEB
RENB
2
RCLKB
RENB
1
GND
Vcc
PAEB
PAFB
DB
0
DB
1
DB
2
DB
3
DB
4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
QA
0
FFA
EFA
OEA
RENA
2
RCLKA
RENA
1
GND
QB
8
QB
7
QB
6
QB
5
QB
4
QB
3
QB
2
QB
1
DA
5
DA
4
DA
3
DA
2
DA
1
DA
0
PAFA
PAEA
WENB
2
/LDB
WCLKB
WENB
1
RSB
DB
8
DB
7
DB
6
DB
5
4093 drw 02
3
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
TM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS
The IDT72V801/72V811/72V821/72V831/72V841/72V851's two FIFOs,
referred to as FIFO A and FIFO B, are identical in every respect. The following
description defines the input and output signals for FIFO A. The corresponding
signal names for FIFO B are provided in parentheses.
Symbol Name I/O Description
DA0-DA8 A Data Inputs I 9-bit data inputs to RAM array A.
D
B0-DB8 B Data Inputs I 9-bit data inputs to RAM array B.
RSA, RSB Reset I When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-
up, a reset of both FIFOs A and B is required before an initial WRITE.
WCLKA Write Clock I Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s)
WCLKB are asserted.
WENA1 Write Enable 1 I If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be
WENB1 used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition
WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and
WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is
LOW.
WENA2/LDA Write Enable 2/ I FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at
WENB2/LDB Load reset, this pin operates as a second Write Enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates
as a control to load and read the programmable flag offsets for its respective array. If the FIFO is configured to have
two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO
A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable
flags, LDA (LDB) is held LOW to write or read the programmable flag offsets.
Q
A0-QA8 A Data Outputs O 9-bit data outputs from RAM array A.
Q
B0-QB8 B Data Outputs O 9-bit data outputs from RAM array B.
RCLKA Read Clock I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1(RENB1) and
RCLKB RENA2 (RENB2) are asserted.
RENA1 Read Enable 1 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH
RENB1 transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
RENA2 Read Enable 2 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to-
RENB2 HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
OEA Output Enable I When OEA (OEB) is LOW, outputs D
A0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the OEB outputs DA0-
D
A8 (DB0-DB8) will be in a high-impedance state.
EFA Empty Flag O When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA
EFB (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
PAEA Programmable O When PAEA (PAEB) is LOW, FIFO A (B) is Almost-Empty based on the offset programmed into the appropriate
PAEB Almost-Empty Flag offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to RCLKA (RCLKB).
PAFA Programmable O When PAFA (PAFB) is LOW, FIFO A (B) is Almost-Full based on the offset programmed into the appropriate offset
PAFB Almost-Full Flag register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
FFA Full Flag O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is
FFB HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
V
CC Power +3.3V power supply pin.
GND Ground 0V ground pin.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

72V841L15PFI

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Buy 72V841L15PFI
Manufacturer:
IDT
Description:
FIFO 3.3 V DUAL 4K X 9
Lifecycle:
New from this manufacturer.
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