TCC−202
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10
Turbo−Charge Mode
The TCC−202 control IC has a Turbo−Charge mode that
significantly shortens the system settling time when
changing programming voltages. In Turbo−Charge mode
the DAC output target voltage is temporarily set to either a
delta voltage above or a delta voltage below the actual
desired target for the TCDLY time. It is recommended that
V
HV
be set to 24 V when using Turbo−Charge mode.
Glide Mode
Unlike turbo mode, which is intended to reduce the
charging time, the glide mode extends the transition time of
each DAC output. Each DAC has an individual control for
turbo mode, glide mode or regular voltage switching. The
glide mode can be enabled for a particular DAC through the
INDEX register, by setting DAC State to ‘1’ when glide
mode is enabled, turbo mode is off for a particular DAC, but
one DAC can be gliding while the other is turbo.
During glide mode the output voltage of a DAC is either
increased or decreased to its set end point, in max 255 steps,
where each DAC time step can be programmed between
2 ms to 64 ms. For programming the glide mode refer to the
application note (coming soon). A programming input is not
required to maintain a glide transition, all step controls are
maintained by the part. Only the inputs to define the glide
need to be programmed.
RF Front−End Control Interface (MIPI RFFE Interface)
The TCC−202 is a read/write slave device which is fully
compliant to the MIPI Alliance Specification for RF
Front−End Control Interface (RFFE) Version 1.10.00 26
July 2011. This device is rated at full−speed operation for
1.62 V<VIO<1.98 V.
Figure 9. MIPI−RFFE Signal Timing during Master Writes to PTIC Control IC
CLK
DATA
TD
SETUP
TD
HOLD
TD
SETUP
TD
HOLD
Figure 10. MIPI−RFFE Signal Timing during Master
Reads from PTIC Control IC
Figure 11. Bus Park Cycle Timing
when MIPI−RFFE Master Reads
from PTIC Control IC
CLK
DATA
T
READ_ACCESS
T
SDATAOTR
T
SDATAOTR
T
READ_ACCESS
CLK
DATA
Bus Park Cycle
T
SDATAZ
TCC−202
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11
Table 10. MIPI RFFE INTERFACE SPECIFICATION
(T
A
= −30 to +85°C; 2.3 V < VDDA < 5.5 V; 1.62 < VIO < 1.98 V; unless otherwise specified)
Parameter
Description Min Typ Max Unit Comments
F
SCLK
Clock Full−Speed
Frequency
0.032 26 MHz Full−Speed Operation:
1.62 V< VIO < 1.98 V
T
SCLK
Clock Full−Speed Period 0.038 32
ms
Full−Speed Operation:
1.62 V< VIO < 1.98 V
T
SCLKIH
CLK Input High Time 11.25 ns Full−Speed
T
SCLKIL
CLK Input Low Time 11.25 ns Full−Speed
TD
SETUP
Write DATA Setup Time −1 1 ns Full−Speed
TD
HOLD
Write DATA Hold Time −5 5 ns Full−Speed
T
READ_ACCESS
Read DATA valid from
CLK rising edge
7.11 ns Full Speed at VIO = 1.80 V,
= 25°C and max 15 pF load on
DATA pin
T
READ_ACCESS
Read DATA valid from
CLK rising edge
9.11 ns Full Speed at VIO = 1.80 V,
= 25°C and max 50 pF load on
DATA pin
The control IC contains thirteen 8−bit registers. Register content is described in Table 11. Some additional registers
implemented as provision, are not described in this document.
Table 11. MIPI RFFE ADDRESS MAP
Register
Address
Description Purpose
Access
Type
Size (bits)
0x00 DAC Configuration (Enable Mask) High voltage output enable mask Write 7
0x01 Turbo Register DAC A, B Turbo−charge configuration DAC A, B (Note 2) Write 8
0x02 DAC A Register OUT A value [6:0] Write 8
0x03 DAC B Register OUT B value [6:0] Write 8
0x09 Wake Up Wake−Up Controls Write 8
0x10 Boost Voltage (VHV) Settings for the boost high voltage Write 8
0x12 Turbo−Charge Delay DAC A, B Turbo−charge delay steps
DAC A, B
Write 8
0x13 Turbo−Charge Delay DAC A, B Turbo−charge delay, multiplication
DAC A, B
Write 8
0x1A MIPI−RFFE STATUS Detect MIPI protocol errors Read/Write 8
0x1B RFFE Group SID MIPI RFFE group slave Write 8
0x1C Power Mode and Trigger Register Power mode & trigger control Write 8
0x1D Product ID Register Product number (Notes 3 and 5) Write 8
0x1E Manufacturer ID Register MN (10 bits long)
Manufacturer ID[7:0] (Note 4)
Write 8
0x1F Unique Slave Identifier Register (USID) Spare [7:6]
[5,4] = Manufacturer ID [9:8]
Write 8
0x2C Glide Timer Settings [6:5] Turbo and Glide control / [4:0] Glide Timer
setting / Need extended write for this register
Write 8
2. The details for configuration of Turbo mode should be ascertained from the Programming Guide, available from ON Semiconductor.
3. The two least significant bits from Product ID register are programmed in OTP during manufacture. The other six bits of Product ID are
hardcoded in ASIC.
4. Manufacture ID is hardcoded in ASIC, and mapped in a READ−only register, not programmed in OTP.
5. TCC−202 supports WRITE access to Product ID, only in respect to comply with MIPI RFFE specification 6.8.3, Programmable USID”, of
MIPI Alliance Specification for RF Front−End Control Interface (RFFE) Version 1.00.00 26 July 2011.
TCC−202
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12
Table 12. REGISTER DETAILS The following are the details of the available RFFE registers:
Register RFFE:
RFFE_REG_0x00 Address RFFE A[4:0]: 0x00
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
6 5 4 3 2 1 0
Bits SS Enable Reserved Reserved DAC A (Note 6) DAC B (Note 6) Reserved Reserved
Reset W−1 U−0 U−0 W−0 W−0 U−0 U−0
6. When any of the bits [3:2] are written with ‘0’, the corresponding DAC is disabled, but the Turbo−Charge process which is already started, will
not be stopped.
7. If all bits [3:2] are ‘0’, then incoming DAC messages will be ignored, until at least one of [3:1] is set ‘1’.
Bit [6]: Spread Spectrum enable
0: SS disabled
1: SS enabled
Bit [3]: Control DAC A
0: off (default)
1: enabled
Bit [2]: Control DAC B
0: off (default)
1: enabled
Register RFFE:
RFFE_REG_0x01 Address RFFE A[4:0]: 0x01
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits Reserved
Reset W−0 W−0 W−0 W−0 W−0 W−0 W−0 W−0
Register RFFE: RFFE_REG_0x02 Address RFFE A[4:0]: 0x02
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits Reserved DAC A value [6:0]
Reset U−0 W−0 W−0 W−0 W−0 W−0 W−0 W−0
Register RFFE: RFFE_REG_0x03 Address RFFE A[4:0]: 0x03
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits Not Used DAC B value [6:0]
Reset W−0 W−0 W−0 W−0 W−0 W−0 W−0 W−0
TC_STP_DACx [1:0] Turbo Steps for TCDLY [us]
00 3
01 (default) 5
10 7
11 9
Register RFFE: RFFE_REG_0x12 Address RFFE A[4:0]: 0x12
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits Reserved Reserved TC_STP_DAC_B TC_STP_DAC_A
Reset U−0 U−0 U−0 U−0 W−0 W−1 W−0 W−1

TCC-202A-RT

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Tuners 0TCCA BUMPED DIE WLC
Lifecycle:
New from this manufacturer.
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