TCC−202
www.onsemi.com
4
Table 3. RECOMENDED OPERATING CONDITIONS
Symbol Parameter
Rating
Unit
Min Typ Max
T
AMB_OP
Operating Ambient Temperature −30 +85 °C
T
J_OP
Operating Junction Temperature −30 +125 °C
AVDD Analog Supply Voltage 2.3 5.5 V
VIO IO Reference Supply Voltage 1.62 1.98 V
Table 4. DC CHARACTERISTICS (T
A
= −30 to +85°C; V
OUTX
= 15 V for each output; 2.3 V < AVDD < 5.5 V; 1.62 V < VIO < 1.98 V;
R
LOAD
= equivalent series load of 5.6 kW and 2.7 nF; C
HV
= 47 nF; L
BOOST
= 15 mH; unless otherwise specified)
Symbol
Parameter Min Typ Max Unit Comment
SHUTDOWN MODE
I
AVDD
AVDD Supply Current 1.5 mA
VIO Supply is Low
I
L_BOOST
L_BOOST Leakage 1.5
I
BATT
Battery Current 2.5
I
VIO
VIO Supply Current −1 1
I
CLK
CLK Leakage −1 1
I
DATA
DATA Leakage −1 1
ACTIVE MODE
I
BATT_SS0
Average battery current, 2 outputs @
0 V steady state
380 750
mA
At VHV = 20 V
AVDD = 3.3 V
I
BAT_SS2
Average battery current, 2 outputs @
2 V steady state
400 780 mA At VHV = 20 V
AVDD = 3.3 V
I
BATT_SS16
Average battery current, 2 outputs @
16 V steady state
510 870 At VHV = 20 V
AVDD = 3.3 V
I
L_BOOST_SS0
Average inductor current, 2 outputs @
0 V steady state
260 490 At VHV = 20 V
AVDD = 3.3 V
I
L_BOOST_SS2
Average inductor current, 2 outputs @
2 V steady state
280 510 At VHV = 20 V
AVDD = 3.3 V
I
L_BOOST_SS16
Average inductor current, 2 outputs @
16 V steady state
400 600 At VHV = 20 V
AVDD = 3.3 V
I
VIO_INACT
VIO average inactive current 3 VIO is high, no bus activity
I
VIO_ACTIVE
VIO average active current 250 VIO = 1.8 V, master sending
data at 26 MHz
V
VREG
1.7 1.9 V No external load allowed
LOW POWER MODE
I
AVDD
AVDD Supply Current 8 mA
I
L_BOOST
L_BOOST Leakage 6
I
BATT
Battery Current 14 I
AVDD
+ I
L_BOOST
I
VIO
VIO Supply Current 3 No bus activity
V
VREG
1.6 1.9 V No external load allowed
TCC−202
www.onsemi.com
5
Table 5. BOOST CONVERTER CHARACTERISTICS
(AVDD from 2.3 V to 5.5 V; VIO from 1.62 V to 1.98 V; T
A
= –30 to +85°C; C
HV
= 47 nF; L
BOOST
= 15 mH; unless otherwise specified)
Symbol
Parameter Conditions Min Typ Max Unit
VHV_min Minimum programmable output volt-
age (average), DAC Boost = 0h
Active mode 13
V
VHV_max Maximum programmable output volt-
age (average), DAC Boost = Fh
Active mode 28
Resolution Boost voltage resolution 4−bit DAC 1
I
L_BOOST_LIMIT
Inductor current limit 200 mA
Table 6. ANALOG OUTPUTS (OUT A, OUT B)
(AVDD from 2.3 V to 5.5 V; VIO from 1.62 V to 1.98 V; VHV = 26 V; T
A
= –30 to +85°C; Rload = unless otherwise specified)
Parameter
Description Min Typ Max Unit Comment
SHUTDOWN MODE
Z
OUT
OUT A, OUT B output impedance 7
MW
DAC disabled
ACTIVE MODE
V
OH
Maximum output voltage 23.8 V DAC A, B = 7Fh,
DAC Boost = Fh, I
OH
< 10 mA
V
OL
Minimum output voltage 1 V DAC A, B = 01h, DAC
Boost = 0h to Fh, I
OH
< 10 mA
Slew Rate 3 10
ms
2 V to 24 V step, measured at
V
OUT
= 15.2 V,
R
LOAD
= equivalent series load of
2.7 kW and 5.6 nF, Turbo enabled
R
PD
OUT A, OUT B set in pull−down
mode
1000
W
DAC A, B = 00h, DAC Boost = 0h to
Fh, selected output(s) is disabled
Resolution Voltage resolution (1−bit) 188 mV (1 LSB = 1−bit)
V
OFFSET
Zero scale, least squared best fit −1 +1 LSB
Error −3.0 +3.0 %V
OUT
Over 2 V – 24 V V
O
range
DNL Differential non−linearity least
squared best fit
−0.9 +0.9 LSB Over 2 V – 24 V V
O
range
INL Integral non−linearity least squared
best fit
−1 +1 LSB Over 2 V – 24 V V
O
range
I
SC
Over current protection 5 65 mA Any DAC output shorted to ground
V
RIPPLE
Output ripple with all outputs at
steady state
40 mV RMS Over 2 V – 24 V for VHV = 23.5 V
TCC−202
www.onsemi.com
6
THEORY OF OPERATION
Overview
The control IC outputs are directly controlled by
programming the two DACs (DAC A and DAC B) through
the digital interface.
The DAC stages are driven from a reference voltage,
generating an analog output voltage driving a high−voltage
amplifier supplied from the boost converter (see Figure 1
Control IC Functional Block Diagram).
The control IC output voltages are scaled from 0 V to
24 V, with 128 steps of 188 mV (2x (24 / 255 V) =
0.188235 V). The nominal control IC output can be
approximated to 188 mV x DAC value.
For performance optimization the boost output voltage
(VHV) can be programmed to levels between 13 V and 28 V
via the DAC_boost register (4 bits with 1 V steps). The
startup default level for the boosted voltage is VHV = 24 V.
For proper operation and to avoid saturation of the output
devices and noise issues it is recommended to operate the
boosted VHV voltage at least 2 V above the highest
programmed V
OUT
voltage of any of the two outputs.
Operating Modes
The following operating modes are available:
1. Shutdown Mode: All circuit blocks are off, the
DAC outputs are disabled and placed in high Z
state and current consumption is limited to
minimal leakage current. The shutdown mode is
entered upon initial application of AVDD or upon
VIO being placed in the low state. The contents of
the registers are not maintained in shutdown mode.
2. Startup Mode: Startup is only a transitory mode.
Startup mode is entered upon a VIO high state. In
startup mode all registers are reset to their default
states, the digital interface is functional, the boost
converter is activated, outputs OUT A and OUT B
are disabled and the DAC outputs are placed in a
high Z state. Control software can request a full
hardware and register reset of the TCC−202 by
sending an appropriate PWR_MODE command to
direct the chip from either the active mode or the
low power mode to the startup mode. From the
startup mode the device automatically proceeds to
the active mode.
3. Active Mode: All blocks of the TCC−202 are
activated and the DAC outputs are fully controlled
through the digital interface, DACs remain off
until enabled. The DAC settings can be
dynamically modified and the HV outputs will be
adjusted according to the specified timing
diagrams. Each DAC can be individually
controlled and/or switched off according to
application requirements. Active mode is
automatically entered from the startup mode.
Active mode can also be entered from the low
power mode under control software command.
4. Low Power Mode: In low power mode the serial
interface stays enabled, the DAC outputs are
disabled and are placed in a high Z state and the
boost voltage circuit is disabled. Control software
can request to enter the low power mode from the
active mode by sending an appropriate
PWR_MODE command. The contents of all
registers are maintained in the low power mode.
Shutdown
Startup
(Registers reset)
Active
Low Power
(User Defined)
PWR_MODE = 0b10
VDDA = 0
Figure 3. Modes of Operation
Battery insertion
(User Defined)
PWR_MODE =
0b01
automatic
VIO = HIGH
VIO = LOW
VIO = LOW
PWR_MODE = 0b00
PWR_MODE =
0b01

TCC-202A-RT

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Tuners 0TCCA BUMPED DIE WLC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet