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TCC-202A-RT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
TCC−202
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16
Register RFFE:
RFFE_PRODUCT_ID_0x1D Address RFFE A[4:0]: 0x1D
Reset Source: N/A
7 6 5 4 3 2 1 0
Bits PID7 PID6 PID5 PID4 PID3 PID2 PID1 PID0 (1)
Reset 0 0 1 0 0 0 0 OTP[4]
Bits [7:1] are hardcoded in ASIC
Bits [0] can be programmed in OTP during manufacturing
Register RFFE: RFFE_MANUFACTURER_ID_0x1E Address RFFE A[4:0]: 0x1E
Reset Source: N/A
7 6 5 4 3 2 1 0
Bits MPN7 MPN6 MPN5 MPN4 MPN3 MPN2 MPN1 MPN0
Reset 0 0 1 0 1 1 1 0
Register RFFE: RFFE_USID_0x1F Address RFFE A[4:0]: 0x1F
Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits Reserved (2) MPN9 (2) MPN8 (2) USID3 (1) USID2 (1) USID1 (1) USID0 (1)
Reset 0 0 0 1 W−0 W−1 W−1 W−1
USID = Unique Slave Identifier Register
1. USID field can be changed by:
• MIPI−RFFE broadcast messages when USID field within the Register Write Command is 0b0000
• MIPI−RFFE individual messages when USID field within the Register Write Command equal with content of
RFFE_REG_0x1F[3:0]
2. In the sequence of writing USID field, the upper [7:4] must match the value 0b0001 hardcoded in the RFFE register
0x1F
NOTE: USID value is NOT retained during SHUTDOWN power mode.
NOTE: USID value is not affected by SWR bit from RFFE_STATUS register.
TCC−202
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17
Register 0 Write Command Sequence
The Command Sequence starts with an SSC which is followed by the Register 0 Write Command Frame. This Frame contains
the Slave address, a logic one, and the seven bit word that will be written to Register 0. The Command Sequence is depicted
below.
Figure 12. Register 0 Write Command Sequence
Table 13. RFFE COMMAND FRAME FOR REGISTER 0 WRITE COMMAND SEQUENCE
Description SSC Command Frame
DAC Configuration 1 0 SA (3,0) 1 0 0 0 0 0 0 0 P BP
Register Write Command Sequence
The Write Register command sequence may be used to access each register (addresses 0−31).
Figure 13. Register Write Command Sequence
Table 14. RFFE COMMAND FRAME FOR REGISTER WRITE COMMAND SEQUENCE for DACs Loading Procedure
Description SSC Command Frame Data Frame BP
Turbo Charge Settings 1 0 SA (3,0) 0 1 0 0 0 0 0 1 P Turbo charge (7:0) P BP
Register Write DAC A 1 0 SA (3,0) 0 1 0 0 0 0 1 0 P DAC_A (6:0) P BP
Register Write DAC B 1 0 SA (3:0) 0 1 0 0 0 0 1 1 P DAC_B (6:0) P BP
TCC−202
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18
This sequence can be used for Read/Write procedure for some other purposes as shown on the following table:
Table 15. OTHER RFFE COMMAND SEQUENCES
Description SSC Command Frame Data Frame
Active Mode 1 0 SA (3,0) 0 1 0 1 1 1 0 0 P 0 0 X X X X X X BP
Startup Mode 1 0 SA (3,0) 0 1 0 1 1 1 0 0 P 0 1 X X X X X X BP
Low Power 1 0 SA (3:0) 0 1 0 1 1 1 0 0 P 1 0 X X X X X X BP
Reserved 1 0 SA (3,0) 0 1 0 1 1 1 0 0 P 1 1 X X X X X X BP
Product ID 1 0 SA (3,0) 0 1 0 1 1 1 0 1 P 0 0 1 0 0 0 0 0/1 BP
Manufacturer ID 1 0 SA (3:0) 0 1 0 1 1 1 1 0 P 0 0 1 0 1 1 1 0 BP
Manufacturer USID 1 0 SA (3,0) 0 1 0 1 1 1 1 1 P 0 0 0 1 USID BP
Extended Register Write Command Sequence
In order to access more than one register in one sequence
this message could be used. Most commonly it will be used
for loading three DAC registers at the same time. The four
LSBs of the Extended Register Write Command Frame
determine the number of bytes that will be written by the
Command Sequence. A value of 0b0000 would write one
byte and a value of 0b1111 would write sixteen bytes.
If more than one byte is to be written, the register address
in the Command Sequence contains the address of the first
extended register that will be written to and the Slave’s local
extended register address shall be automatically
incremented by one for each byte written up to address 0x1F,
starting from the address indicated in the Address Frame.
Figure 14. Extended Register Write Command Sequence
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

TCC-202A-RT

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Manufacturer:
ON Semiconductor
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Tuners 0TCCA BUMPED DIE WLC
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