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TCC-202A-RT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
TCC−202
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13
Register RFFE:
RFFE_REG_0x13 Address RFFE A[4:0]: 0x13
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits Reserved Reserved TCM_B TCM_A
Reset U−0 U−0 U−0 U−0 W−0 W−0 W−0 W−0
TCM [1:0] Turbo Multiplication Factor
00 (default) 4
01 3
10 2
11 1
Step [us] DAC state 0 1 2 3 4 5 6 7 8 9 10 11
9 TCDLY Turbo OFF 18 27 36 45 54 63 72 81 90 99
7 TCDLY Turbo OFF 14 21 28 35 42 49 56 63 70 77
5 (default) TCDLY Turbo OFF 10 15 20 25 30 35 40 45 50 55
3 TCDLY Turbo OFF 6 9 12 15 18 21 24 27 30 33
The value of Turbo time is deducted based on the hardware comparison of new DAC value in respect to old DAC value, as follows:
If DAC new > DAC old, then T
UP = TCDLY
If DAC new < DAC old, and DAC new_divby2 < 21, then T
DOWN = TCDLY + TCM * (21 – DAC_new_divby2) If DAC new < DAC old, and
DAC new_divby2 > 21, then T
DOWN = TCDLY
If DAC new < DAC old, and DAC new_divby2 = 21, then T
DOWN = TCDLY
Register RFFE:
RFFE_REG_0x9 Address RFFE A[4:0]: 0x09
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits
Reserved DAC_WAKEUP_CTRL
Turbo Latency Select
Reserved Reserved
Reset U−0 U−0 U−0 U−0 W−0 W−0 W−0 W−0
Bit [3]: DAC Wake−up Control applicable to Wake−up from LP
0 : (default) Don’t apply Turbo when Wake−up from LP STD or LP FTA
1: Always apply Turbo UP when Wake−up from LP STD or LP FTA. Turbo UP is calculated based on DAC value prior to
enter LP STD or LP FTA mode.
NOTE 1: Turbo is NOT applied after Wake−up to the DACs which are programmed with 0x00 in the DAC value register
NOTE 2: Turbo is NOT applied after Wake−up from FTA mode if a trigger (Turbo, Normal, Glide) was generated while TC2x2
was in LP FTA mode
NOTE 3: When Bit[3] = ‘1’, then Turbo is applied after Wake−up regardless if:
• DAC values are updated or not
• last DAC value update is equal with old DAC value
NOTE 4: When RFFE_REG_0x31 / Wake−up DAC Ctrl is ‘0’ (default) Turbo after Wake−Up is applied after first
vhv_too_lowfalling edge is detected. When RFFE_REG_0x31 / Wake−up DAC Ctrl is ‘1’ Turbo after Wake−up is applied
after rc_clk starts.
Bit [2]: Turbo UP latency Select when Wake−up from LP.
This field has no effect when DAC_WAKEUP_CTRL[1:0] = ‘00’
0: (default) Turbo UP latency is 50 ms
1: Turbo UP latency is 100 ms
TCC−202
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14
Register RFFE:
RFFE_REG_0x10 Address RFFE A[4:0]: 0x10
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits Reserved Fixed Boost voltage value
Reset U−0 U−0 U−0 U−1
W-1
W−0
W-1 W-1
Bit [3:0]: Boost voltage value
Register RFFE: RFFE_STATUS_0x1A Address RFFE A[4:0]: 0x1A
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits SWR CFPE CLE AFPE DFPE RURE WURE BGE
Reset W−0 R−0 R−0 R−0 R−0 R−0 R−0 R−0
RFFE_STATUS register can be read any time after power−up without the need to enable the Read Operation as described
below.
SWR Soft−Reset MIPI−RFFE registers
Write ‘1’ to this bit to reset all the MIPI−RFFE registers, except RFFE_REG_0x1C, RFFE_USID, and RFFE_GROUP_SID
This bit will always Read−back ‘0’.
The soft reset occurs in the last clock cycle of the MIPI−RFFE frame which Writes ‘1’ to this bit.
Right immediately after this frame, all the MIPI−RFFE registers have the reset value and are ready to be reprogrammed as
desired.
The OTP duplicated registers are reset to the values written in OTP.
SWR can be written only by USID messages. GSID and Broadcast frames will be ignored when writing to this register field.
RFFE_STATUS Bits [6:0] are set ‘1’ by hardware to flag when a certain condition is detected, as described below.
RFFE_STATUS Bits [6:0] cannot be written, but it is cleared to ‘0’ under following conditions:
• Hardware Self−reset is applied after RFFE_STATUS is READ
• When SWR is written ‘1’ with USID frames
• When power mode transitions through STARTUP mode ‘01’
• After Power−up Reset
CFPE
1: Command frame with parity error received.
On the occurrence of this error, the slave will ignore the entire Command Sequence
CLE
1: Incompatible command length, due to unexpected SSC received before command length to be completed.
On the occurrence of this error, the slave will accept Write data up to the last correct and complete frame. When MIPI−RFFE
multi−byte Read command is detected, the slave will always replay with an extended Read command of length of one byte.
AFPE
1: Address frame with parity error received.
On the occurrence of this error, the slave will ignore the entire Command Sequence
DFPE
1: Data frame with parity error received.
On the occurrence of this error, the slave will ignore only the erroneous data byte (s)
RURE
1: Read of non−existent register was detected.
On the occurrence of this error, the slave will not respond to the Read command frame.
When the Read Operation is not enabled ,any read from an address other than 0x1A, will set RURE and the slave will not
respond to the Read command frame.
When the Read Operation is enabled , any read from an unoccupied RFFE register address will set RURE.
WURE
1: Write to non−existent register was detected.
On the occurrence of this error, the slave discards data being written, and on the next received frame, proceeds as normal
BGE
1: Read using the Broadcast ID was detected
On the occurrence of this error, the slave will ignore the entire Command Sequence
TCC−202
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15
Register RFFE:
RFFE_GROUP_SID_0x1B Address RFFE A[4:0]: 0x1B
Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1 0
Bits Reserved Reserved Reserved Reserved GSID[3] GSID[2] GSID[1]
GSID[0]
Reset 0 0 0 0 W−0 W−0 W−0 W−0
GSID = Group Slave Identifier Register
NOTE: The GSID[3:0] field can be written directly by messages using USID.
NOTE: GSID value is NOT retained during SHUTDOWN power mode.
NOTE: GSID value is not affected by SWR bit from RFFE_STATUS register
NOTE: Frames using USID = GSID, can write only to RFFE_REG_0x1C[7:6] and [2:0].
NOTE: RFFE READ frames containing GSID will be ignored
Register RFFE:
RFFE_REG_0x1C Address RFFE A[4:0]: 0x1C
Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)
7 6 5 4 3 2 1
0
Bits
Power Mode
(Note 12)
Trigger Mask 2
(Notes 8, 9, 10, 11)
Trigger Mask 1
(Notes 8, 9, 10, 11)
Trigger Mask 0
(Notes 8, 9, 10, 11)
Trigger 2 Trigger 1
Trigger 0
Reset W−0 W−0 W−0 W−0 W−0 W−0 W−0 W−0
8. Trigger Mask bits [5:3] can be changed, either set or cleared, only with an individual message using USID
9. During broadcast MIPI−RFFE accesses using GSID = ‘0000’, Trigger bits [2:0] are masked by the pre−existent setting of Trigger Mask Bits
[5:3]
10.During Individual MIPI−RFFE accesses using USID, Trigger bits [2:0] are masked by the incoming Trigger Mask bits [5:3] within the same
write message to RFFE_REG_0x1C register. During Individual MIPI−RFFE accesses using USID, pre−existent setting of Trigger Mask Bits
[5:3] is ignored.
11. When RFFE_REG_0x1C/ Trigger_Mask_2 = ‘1’ and Trigger_Mask_1 = ‘1’ and Trigger_Mask_0 = ‘1’, then DAC messages will be sent to
DACs immediately after RFFE_REG_0x04 is received, without waiting for any trigger
12.Power mode field bits [7:6] and Triggers bits [2:0] can be changed by either MIPI−RFFE broadcast messages when USID field within the
Register Write Command is 0x0 , or individual messages when USID fields within the Register Write Command is equal with
RFFE_REG_0x1F[3:0]
NOTE: All the 8 bits of RFFE_REG_0x1C register bits are NOTaffected by SWR bit from RFFE_STATUS register
Bit [7:6]: Power Mode
00: ACTIVE mode, defined by following hardware behavior:
• Boost Control active, VHV set by Digital Interface
• Vout A and B enabled and controlled by Digital Interface
01: STARTUP mode, defined by following hardware behavior: o
• Boost Control active, VHV set by Digital Interface
• Vout A and B disabled
10: LOW POWER mode is defined by following hardware behavior:
• Digital interface is active, while all other circuits are in lowpower mode
11: Reserved (State of hardware does not change)
Bit 5: Mask trigger 2
0:Trigger 2 not masked. Data goes to destination register after bit 2 is written value 1 (default)
1:Trigger 2 is masked. Data goes directly to the destination register
Bit 4: Mask trigger 1
0:Trigger 1 not masked. Data goes to destination register after bit 1 is written value 1(default)
1:Trigger 1 is masked. Data goes directly to the destination register.
Bit 3: Mask trigger 0
0:Trigger 0 not masked. Data goes to destination register after bit 0 is written value 1(default)
1:Trigger 0 is masked. Data goes directly to the destination register.
Bit 2: Trigger 2
Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 5.
Bit 1: Trigger 1
Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 4.
Bit 0: Trigger 0
Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 3.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

TCC-202A-RT

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Buy TCC-202A-RT
Manufacturer:
ON Semiconductor
Description:
Tuners 0TCCA BUMPED DIE WLC
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