ICS85314AGI-11 REVISION F SEPTEMBER 16, 2013 15 ©2013 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS85314I-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314I-11 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for V
CC
= 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.8V * 80mA = 304mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
Total Power_
MAX
(3.6V, with all outputs switching) = 304mW + 150mW = 454mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow or 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.454W * 66.6°C/W = 115°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance
JA
for 20 Lead SOIC, Forced Convection
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. Thermal Resistance
JA
for 20 Lead TSSOP, Forced Convection
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
JA
by Velocity
Linear Feet per Minute 0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W
JA
by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
