OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

85314AGI-11LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
ICS85314AGI-11 REVISION F SEPTEMBER 16, 2013 16 ©2013 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 7.
Figure 7. LVPECL Driver Circuit and Termination
To calculate power dissipation due to loading, use the following equations which assume a 50 load, and a termination voltage of V
CC
– 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CC_MAX
– V
OH_MAX
) = 0.9V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CC_MAX
– V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L]
* (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω
ICS85314AGI-11 REVISION F SEPTEMBER 16, 2013 17 ©2013 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Reliability Information
Table 7A.
JA
vs. Air Flow Table for a 20 Lead SOIC, Forced Convection
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Table 7B.
JA
vs. Air Flow Table for a 20 Lead TSSOP, Forced Convection
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS85314I-11 is: 674
JA
by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W
JA
by Velocity
Linear Feet per Minute 0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
ICS85314AGI-11 REVISION F SEPTEMBER 16, 2013 18 ©2013 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Package Outlines and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8A. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
Package Outline - M Suffix for 20 Lead SOIC
Table 8B. Package Dimensions for 20 Lead SOIC
Reference Document: JEDEC Publication 95, MS-013, MS-119
All Dimensions in Millimeters
Symbol Minimum Maximum
N 20
A 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 6.40 6.60
E 6.40 Basic
E1 4.30 4.50
e 0.65 Basic
L 0.45 0.75
0° 8°
aaa 0.10
300 Millimeters
All Dimensions in Millimeters
Symbol Minimum Maximum
N 20
A 2.65
A1 0.10
A2 2.05 2.55
B 0.33 0.51
C 0.18 0.32
D 12.60 13.00
E 7.40 7.60
e 1.27 Basic
H 10.00 10.65
h 0.25 0.75
L 0.40 1.27
0° 7°
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

85314AGI-11LF

Mfr. #:
Buy 85314AGI-11LF
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1-to-5 Diff -to-2.5V/3.3V LVPECL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet