NCP81022
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17
SVI2 INTERFACE
SVD SERIAL PACKET BIT DESCRIPTION
Bit Default Description
1:5 11000 Start code
6 1 VDD domain selector bit, if set then the following two data bytes contain the VID for VDD,
the PSI state for VDD and the loadline slope trim and offset
7 0 VDDNB domain selector bit, if set then the following two data bytes contain the VID for
VDD, the PSI state for VDDNB and the loadline slope trim and offset
8 0
9 0 ACK
10 0 PSI0 power state indicator level 0. when this signal is asserted the NCP81022 is in a lower
power state, and phase shedding is initialized.
11:17 XXXXXXX VID code [7:1] see table 2
18 0 ACK
19 X VID code LSB [0] see table 2
20 PSI1, when this bit is asserted the NCP81022 is in a low power state and operated in diode
mode emulation mode
21 1 TFN, this is an active high signal that allows the processor to control the telemetry function-
ality of the NCP81022.
22:24 011 Loadline slope Trim [2:0]
25:26 10 Offset Trim [1:0]
27 0 ACK
1
SVC
SVD
10
0
0
START SEQUENCE
DOMAIN
SELECTION
1
10
18
9
0+
ACK
PSI0
VID CODE BIT 7:1
ACK
VID
CODE
BIT 0
PSI1
TFN
27
LOADLINE
SLOPE TRIM
OFFSET
TRIM
ACK
STOP
Figure 4. SVD Packet Structure
SVI2 Interface
The NCP81022 is design to accept commands over AMD’s SVI2 bus. The communication is accomplished using three lines,
a data line SVD, a clock line SVC and a telemetry line SVT. The SVD line can be used not only to set the voltage level of the
Main rail and North bridge rail, but can also set the load line slope, programmed offset and also the PSI (power state indicator
bits). The SVT line from the NCP81022 communicates voltage, current and status updates back to the processor.
Power State Indicator (PSI)
The SVI2 protocol defines two PSI levels, PSI0 and PSI1. These are active low signals which indicate when the NCP81022
can enter low power states to improve system efficiency and performance. Increasing levels of PSI state indicates low current
consumption of the processor.
