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NCP81022MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
NCP81022
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22
SVC
SVD
SVT
TSVD−STO Pt o SVT−STA RT
TRISING EDGE SVCto SVD−START
Figure 9. SVT start and Stop timing
Table 2. SVI2 BUS TIMING PARAMETERS FOR 3.33 MHz OR 20 MHz OPERATION
Parameter Min Max Unit
T
PERIOD
50 TDC ns
SVC Frequency TDC 20 MHz
T
HIGH
SVC High Time 20 ns
T
Low
SVC Low Time 30 ns
T
setup
(SVD, SVT Setup time to SVC rise edge) 5 10 ns
T
Hold
( SVD, SVT Hold time from SVC falling edge) 5 10 ns
T
Quiet
(Time neither processor nor VR is driving the SVD line) 10 ns
T
ZACK
( total time processor tristates SVD) 50 ns
T
START
20 ns
T
STOP
10 ns
T
ReSTART
(Time Between Stop and Start on SVD) 50 ns
T
ReSTART
(Time Between Stop and Start on SVD) 50 ns
T
SVD−STOP
to
SVT−START
(Time Between SVD stop and SVT Start) 80 ns
T
Rising
Edge
SVC
to
SVTD−Start
(Time between Rising Edge of SVC after last SVT bit to SVD
start)
20 ns
SVC, SVD, SVT Fall Time VOH_DC to VOL_DC 1 ns
SVC, SVD, SVT Rise Time VOH_DC to VOL_DC 1 ns
T
Skew−SVC−SVD
The skew between SVC, SVD as seen at the NCP81022; dictated by layout
and tested by simulation
1 ns
T
Skew−SVC−SVD
The skew between SVC, SVD as seen at the Processor; dictated by layout
and tested by measurement
2 ns
T
Propagation
The propagation delay of SVC, SVD, SVT; measured from the transmitter to the
receiver
2 ns
SVC glitches filter width. NCP81022’s glitch filter will reject any SVC transition that persists for
shorter periods than this
3 5 ns
Slew Rate
Slew rate is programmable on power up; a resistor from the SR pin to ground sets the slew rate. Each rail can be programmed
independently between 10 mV/ms, see table below for resistor values.
Slew Rate
Resistance (W)
10 mv/ms
10k
20 mv/ms
25k
30 mv/ms
45k
NCP81022
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23
BOOT VOLTAGE PROGRAMMING
The NCP81022 has a VBOOT voltage register that can be externally programmed for both Main Rail and North Bridge
boot−up output voltage. The VBOOT voltage can be programmed when PWROK is deasserted, through the logic levels present
on SVC and SVD. The table below defines the Boot−VID codes
BOOT VOLTAGE TABLE:
SVC SVD Boot Voltage
0 0 1.1
0 1 1.0
1 0 0.9
1 1 0.8
ADDRESSING PROGRAMMING
The NCP81102 supports eight possible SMBus Addresses. Pin 28 (PWM4) is used to set the SMBus Address. On power up
a 10 mA current is sourced from this pin through a resistor connected to this pin and the resulting voltage is measured. The Table
below provides the resistor values for each corresponding SMBus Address. The address value is latched at startup.
Table 3. SMBus ADDRESS
Resistor Value SMBus (Hex)
10k 20
25k 21
45k 22
70k 23
95k 24
125k 25
165k 26
220k 27
Programming the ICC_Max
A resistor to ground on the IMAX pin program the ICC_Max value at the time the NCP81022 in enabled. 10 mA is sourced
from this pin to generate a voltage on the program resistor. The resistor value should be no less than 10k.
R
ICC_MAX
+
(
2 * ICC_MAX
)
(
10m * 256
)
Remote Sense Amplifier
A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of
the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to:
V
DIFF
+
ǒ
V
VSP
* V
VSN
Ǔ
)
ǒ
1.3 V * V
DAC
Ǔ
)
ǒ
V
DROOP
* V
CSREF
Ǔ
This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The
non−inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier
output bias.
High Performance Voltage Error Amplifier
A high performance error amplifier is provided for high bandwidth transient performance. A standard type 3 compensation
circuit is normally used to compensate the system.
Differential Current Feedback Amplifiers
Each phase has a low offset differential amplifier to sense that phase current for current balance and per phase OCP protection
during soft−start. The inputs to the CSREF and CSPx pins are high impedance inputs. It is recommended that any external filter
resistor RCSN not exceed 10 kW to avoid offset issues with leakage current. It is also recommended that the voltage sense
NCP81022
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24
element be no less than 0.5 mW for accurate current balance, user care should be taken in board design if lower DCR inductor
are used as this may affect the current balance in light load conditions. Fine tuning of this time constant is generally not required.
VOUT
21
CCSNRCSN
DCR LPHASE
CSPx
CSREF
R
CSN
+
L
PHASE
C
CSN
* DCR
Figure 10. Differential Current Feedback
The individual phase current is summed into to the PWM comparator feedback in this way current is balanced is via a current
mode control approach.
Total Current Sense Amplifier
The NCP81022 uses a patented approach to sum the phase currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP
and CSREF. The Ref (n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground.
The amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the
inductor series resistance (DCR). Rth is placed near an inductor to sense the temperature of the inductor. This allows the filter
time constant and gain to be a function of the Rth NTC resistor and compensate for the change in the DCR with temperature.
Figure 11. Current Sense Amplifier
The DC gain equation for the current sensing:
V
CSCOMP−CSREF
+ −
Rcs2 )
Rcs1*Rth
Rcs1)Rth
Rph
*
ǒ
Iout
Total
* DCR
Ǔ
Set the gain by adjusting the value of the Rph resistors. The DC gain should set to the output voltage droop. If the voltage
from CSCOMP to CSREF is less than 100mV then it is recommended to increase the gain of the CSCOMP amp and add a
resister divider to the Droop pin filter. This is required to provide a good current signal to offset voltage ratio for the ILIM pin.
When no droop is needed, the gain of the amplifier should be set to provide ~100 mV across the current limit programming
resistor at full load. The values of Rcs1 and Rcs2 are set based on the 220k NTC and the temperature effect of the inductor and
should not need to be changed. The NTC should be placed near the closest inductor. The output voltage droop should be set
with the droop filter divider.
The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit
to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time
constant using commonly available values. It is best to fine tune this filter during transient testing.
F
Z
+
DCR@25° C
2*PI*L
Phase
F
P
+
1
2 * PI *
ǒ
Rcs2 )
Rcs1*Rth@25° C
Rcs1)Rth@25° C
Ǔ
*
(
Ccs1 ) Ccs2
)
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NCP81022MNTXG

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Buy NCP81022MNTXG
Manufacturer:
ON Semiconductor
Description:
Gate Drivers AMD VR CONTROLLER
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