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13. The slave asserts an ACK on SDA after each data byte.
14. After the last data byte the master asserts a STOP condition on SDA
SLAVE
ADDRESS
COMMAND
CODE
DATA
BYTE 1
AAWS
24653178
9
BYTE COUNT
= N
AA
...
10
DATA
BYTE 2
A
...
DATA
BYTE N
PA
11 12 13 14
Extended Write Command
An extended write command is executed with the following format:
1. The master device asserts a START condition on SDA
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA
4. The master sends a command extension code (FEh)
5. The slave asserted ACK on SDA
6. The master sends a command code
7. The slave asserted ACK on SDA
8. The master sends a data byte.
9. The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA and the transaction ends.
S Slave Address
W
A
Command
Extension Code
A
Command
Code
A
1
2
3
4
6
5
7
Data Byte
A
P
8910
The NCP81022 uses the following SMBus read protocols.
Read Byte
In this operation, the master device receives a single byte from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA
7. The master sends the 7 bit slave address followed by the read bit (high)
8. The slave asserts ACK on SDA
9. The slave sends the Data Byte
10. The master asserts NO ACK on SDA.
11. The master asserts a stop condition on SDA and the transaction ends.
SLAVE
ADDRESS
COMMAND
CODE
DATAAAWSAP
24653178
S
SLAVE
ADDRESS
AR
109
11
Read Word
In this operation, the master device receives two data bytes from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
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3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA
7. The master sends the 7 bit slave address followed by the read bit (high)
8. The slave asserts ACK on SDA
9. The slave sends the first Data Byte (low Data Byte)
10. The master asserts ACK on SDA.
11. The slave sends the second Data Byte (high Data Byte)
12. The masters asserts a No ACK on SDA
13. The master asserts a stop condition on SDA and the transaction ends
SLAVE
ADDRESS
COMMAND
CODE
DATA
(LSB)
AAWSA
24653178
S
SLAVE
ADDRESS
AR
109
DATA
(MSB)
AP
1211
13
Block Read
In this operation, the master device sends a command byte, the slave sends a byte count followed by the stated number of
data bytes to the master device as follows:
1. The master device asserts a START condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a REPEATED START condition on SDA
5. The master sends the 7−bit slave address followed by the read bit (high).
6. The slave asserts ACK on SDA
7. The slave sends the byte count N
8. The master asserts ACK on SDA
9. The slave sends the first data byte
10. The master asserts ACK on SDA
11. The slave sends the remainder of the data byes, the master asserts an ACK on SDA after each data byte.
12. After the last data byte the master asserts a No ACK on SDA.
13. The master asserts a STOP condition on SDA
SLAVE
ADDRESS
BYTE COUNT
= N
AWS
2465317
S
SLAVE
ADDRESS
AR
81211
DATA
BYTE N
AP
13
A
DATA
BYTE 1
A
...
109
Extended Read Command
An extended Read byte command is executed with the following format and is shown in figure TBD below:
1. The master device asserts a START condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA
4. The master sends a command extension code (FEh)
5. The slave asserted ACK on SDA.
6. The master sends a command code
7. The slave asserted ACK on SDA.
8. The master sends a REPEATED START condition on SDA
9. The master sends the 7 bit slave address followed by the read bit (high)
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10. The slave asserts ACK on SDA
11. The slave sends the Data Byte
12. The master asserts NO ACK on SDA.
13. The master asserts a stop condition on SDA and the transaction ends.
S Slave Address
W
A
Comm a n d
Extension Code
A
Comm an d
Code
A
1
2
3
4
6
5
7
S Slave Address
R
A
Data Byte
A
P
8
9
10
11 12
13
The NCP81022 includes a timeout feature. If there is no Bus activity for 35 ms, the NCP81022 assumes that the bus is locked
and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers
cannot handle the SMBus timeout feature, so it can be disabled.
To prevent rogue programs or viruses from accessing critical NCP81022 register settings, the lock bit can be set. Setting Bit 0
of the Lock/Reset sets the lock bit and locks critical registers. In this mode, certain registers can no longer be written to until
the NCP81022 is powered down and powered up again. For more information on which registers are locked see the register
map.
REGISTER MAP
CMD
Code
R/W Default Description #Bytes Comment
0x01 R/W 0x80 Operation 1 00xx xxxx – Immediate Off
01xx xxxx – Soft Off
1000 xxxx – On (slew rate set by soft start) – Default
1001 10xx – Margin Low (Act on Fault)
1010 10xx – Margin High (Act on Fault)
0x02 R/W 0x17 ON_OFF_Config 1 Configures how the controller is turned on and off
Bit Default Comment
7:6 00 Reserved for Future Use
5 1 Reserved
4 1 This bit is read only. Switching starts when
commanded by the Control Pin and the Operation
Command, as set in Bits 3:0
3 0 0 : Unit ignores OPERATION commands over the
Interface
1: Unit responds to OPERATION command,
power up may also depend upon Control input, as
described in Bit 2
2 1 0: Unit ignores Main Rail EN pin
1: Unit responds Main Rail EN pin, power up may
also depend upon the Operation Register, as
described for Bit 3
1 1 Control Pin polarity
0 = Active Low
1 = Active High
0 1 This bit is read only. 1 means that when the
controller is disabled it will either immediately turn
off or soft off (as set in the Operation Command)
0x03 W NA Clear_Faults 0 Writing any value to this command code will clear all Status Bits immediately.
0x10 R/W 0x00 Write_Protect 1 The Write_protect command is used to control writing to the device. There is also a lock bit in the
Manufacturer Specification Registers that once set will disable writes to all commands until the
power to the NCP81022 is cycled.
0x19 R 0xB0 Capability 1
This command allows the host to get some information on the SMBus device
Bit Default Comment
7 1 PEC (Packet Error Checking is supported)
6:5 01 Max supported bus speed is 400kHz
4 0 Reverved
3:0 000 Reserved for future use
0x20 R 0x22 Vout_Mode 1 The NCP81022 supports SVI2 VID mode for programming the output voltage

NCP81022MNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers AMD VR CONTROLLER
Lifecycle:
New from this manufacturer.
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