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NCP81022MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
NCP81022
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PHASE DETECTION
Number of
phases
Unused pinsProgramming pin CSNX
2+1 Connect CSN2 and CSN4 to VCC through a 2k resistor.
All other CSN pins connected normally.
Float PWM4 and PWM2
Ground CSP4, and CSP2
1+1 Connect CSN2, CSN3 and CSN4 to VCC through a 2k res-
istor.
All other CSN pins connected normally.
Float PWM4, PWM3 and PWM2
Ground CSP4, CSP3 and CSP2
4+0 CSN1NB pulled to VCC through 2k resistor.
All other CSN pins connected normally.
Float PWM1NB,Ilim NB, Diffout NB, Comp NB, TRB-
STNB and CScompNB
Ground IoutNB, DroopNB, FBNB, CSSUM-
NB,CSPNB and VDDNB
3+0 Connect CSN4 and CSN1NB to VCC through a 2k resistor.
All other CSN pins connected normally.
Float PWM4 PWM1NB,Ilim NB, Diffout NB, Comp
NB, TRBSTNB and CScompNB
Ground CSP4, IoutNB, DroopNB, FBNB, CSSUM-
NB,CSPNB and VDDNB
2+0 Connect CSN2, CSN4 and CSN1NB to VCC through a 2k
resistor.
All other CSN pins connected normally.
Float PWM4, PWM2, PWM1NB,Ilim NB, Diffout NB,
Comp NB, TRBSTNB and CScompNB
Ground CSP4, CSP2 IoutNB, DroopNB, FBNB,
CSSUMNB,CSPNB and VDDNB
1+0 Connect CSN2, CSN3, CSN4 and CSN1NB to VCC through
a 2k resistor.
CSN1 pin connected normally.
Float PWM4, PWM3, PWM2, PWM1NB,Ilim NB,
Diffout NB, Comp NB, TRBSTNB and CScompNB
Ground CSP4, CSP3, CSP2 IoutNB, DroopNB, FB-
NB, CSSUMNB,CSPNB and VDDNB
Protection Features
Output voltage out of regulation is defined as either a UVP or OVP event. The protection mechanism in case of either type
of fault is described in this section.
Gate Driver UVLO Protection
The NCP811022 monitors Vcc and DRON signals during UVLO restart, as shown in Figure 17.
DAC
Gate Driver Pulls DRON
Low during driver UVLO
and Calibration
If DRON is pulled low the
controller will hold off its
startup
Figure 17. Gate Driver UVLO Restart
VCC
UVLO
DRON
Soft Start
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined slew rate programmed on startup. The controller enables and sets the PWM signal to the 2.0 V MID state to
indicate that the drivers should be in diode mode. The COMP pin released to begin soft−start. The DAC will ramp from Zero
to the target DAC codes and the PWM outputs will begin to fire. Each phase will move out of the MID state when the first PWM
pulse is produced preventing the discharge of a pre−charged output.
NCP81022
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Figure 18. Soft−Start Sequence
Over Current Latch− Off Protection
The NCP81022 support IDDSPIKE, an amount of current drawn by the processor that exceeds the sustained design current
limit, TDC, for a thermally significant period of time <10 ms. The NCP81022 incorporates a dual threshold current based
protection mechanism for both the VDD and the VDDNB output to protect the NCP81022 if the output current exceeds TDC.
The NCP81022 provides two different types of current limit protection. During normal operation a programmable total
current limit is provided that scales with the phase count during power saving operation. A second fixed per−phase current limit
is provided for VID lower than 0.25 V, such as during soft−start.
The level of total current limit is set with the resistor from the ILIM pin to CSCOMP pin. Internally the current through ILIM
pin is scaled and then compared to two current thresholds 10 mA and 15 mA, where 10 uA threshold is scaled to indicate the
100% current limit and 15 mA indicates the 150% current limit. If 100% current limit is exceeded, an internal latch−off counter
starts. The controller shuts down if the over current fault is not removed after 50 ms. If 150% current limit is exceeded, the
controller shuts down immediately. To recover from an OCP fault the EN pin must be cycled low. The current limit is scaled
when phase shedding is in operation. Phase shedding from 4−phase to single phase scales the current limit to its 1/4; phase
shedding from 2−phase to single phase scales the current limit to its half.
During startup the per phase current limit is active to protect the individual output stages. This limit monitors the voltage
drop across the DCR through the CSPx and CSREF pins. The minimum threshold is 36 mV.
Under Voltage Monitor
Both output, VDD and VDDNB, must be protected from an under−voltage fault, which is indicative or a short circuit fault.
The UVP threshold is shown in the table below. The output voltage is monitored at the output of the differential amplifier for
UVLO. If the output falls more than 300 mV below the DAC−DROOP voltage the UVLO comparator will trip sending the
VDD_PWRGD/VDDNB_PWRGD signal low. If a UVP event occurs, the NCP81022 need to be re−enable by cycling the
enable pin.
Over Voltage Protection
During normal operation the output voltage is monitored at the differential inputs VSP and VSN. If the output voltage
exceeds the DAC voltage by approximately 325 mV, LGx from integrated drivers will be forced high and PWM/PWMA will
be forced low when OVP is triggered. And then the DAC will ramp down to zero to avoid a negative output voltage spike during
shutdown. When the DAC gets to zero, LGx will be forced high and PWM/PWMA will be forced low with DRON remaining
high. To reset the part the EN pin must be cycled low.
NCP81022
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DAC
VSP_VSN
OVP Threshold
Latch Off
OVP
Triggered
PWM
Figure 19. OVP Threshold Behavior
Parameter Min Typ Max Description
UVP Threshold 300 mV 325 mV 350 mV Voltage below programmed VID
OVP Threshold 300 mV 325 mV 350 mV Voltage below programmed VID
Non−Fault domain
Power down or PWRGD
Delay
1 10
mS
Layout Notes
The NCP81022 has differential voltage and current monitoring. This improves signal integrity and reduces noise issues
related to layout for easy design use. To insure proper function there are some general rules to follow:
Careful layout in per phase and total current sensing are critical for jitter minimization, accurate current balancing and ILIM
monitoring. Give the first priority in component placement and trace routing to per phase and total current sensing circuit. The
per phase inductor current sense RC filters should always be placed as close to the CSREF and CSP pins on the controller as
possible. The filter cap from CSCOMP to CSREF should also be close to the controller. The temperature−compensate resistor
R
TH
should be placed as close as possible to the Phase 1 inductor. The wiring path between R
CSx
and R
PHx
should be kept as
short as possible and well away from switch node lines. The Refx resistors (10 W) connected to CSREF pin should be placed
near the inductors to reduce the length of traces. The above layout notes are shown in the following diagram:
CSCOMP
CSSUM
CSREF
+
−
C
CS1
R
CS1
R
CS2
R
THPlace as close as possible
to nearest inductor
R
PH1
R
PH2
To Switch Nodes
Keep this path as short as
possible and well away
from switch node lines
C
CS2
+
−
+
−
CSP1
CSP2
R
REF1
R
REF2
To V
Sense
OUT
R
CSN1
R
CSN2
C
CSN1
C
CSN2
To
Switch
Nodes
Per phase current sense
RC should be placed
close to CSPx pins
REFx resistors could
be placed near the
inductors to reduce
the number of long
traces
Figure 20.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

NCP81022MNTXG

Mfr. #:
Buy NCP81022MNTXG
Manufacturer:
ON Semiconductor
Description:
Gate Drivers AMD VR CONTROLLER
Lifecycle:
New from this manufacturer.
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