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AD5542ABCPZ-1-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD5512A/AD5542A Data Sheet
Rev. C | Page 4 of 21
AD5542A
V
DD
= 2.7 V to 5.5 V, V
LOGIC
= 2.7 V to 5.5 V, V
REF
= 2.5 V, AGND = DGND = 0 V, −40°C < T
A
< +85°C, unless otherwise noted.
Table 3.
Parameter
1
Min Typ Max Unit Test Condition
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL) ±0.5 ±1.0 LSB B grade
±2.0 A grade
Differential Nonlinearity (DNL)
±0.5
±1.0
Guaranteed monotonic
Gain Error +0.5 ±2 LSB T
A
= 25°C
±3 LSB
Gain Error Temperature Coefficient ±0.1 ppm/°C
Unipolar Zero-Code Error 0.3 ±0.7 LSB T
A
= 25°C
±1.5 LSB
Unipolar Zero-Code Temperature Coefficient ±0.05 ppm/°C
Bipolar Resistor Matching 1.000 Ω/Ω R
FB
/R
INV
, typically R
FB
= R
INV
= 28 kΩ
±0.0015 ±0.0076 % Ratio error
Bipolar Zero Offset Error ±1 ±5 LSB T
A
= 25°C
±6 LSB
Bipolar Zero Temperature Coefficient ±0.2 ppm/°C
Bipolar Zero-Code Offset Error
±1
±5
T
A
= 25°C
±6 LSB
Bipolar Gain Error ±1 ±5 LSB T
A
= 25°C
±6 LSB
Bipolar Gain Temperature Coefficient ±0.1 ppm/°C
OUTPUT CHARACTERISTICS
Output Voltage Range 0 V
REF
− 1 LSB V Unipolar operation
−V
REF
+V
REF
− 1 LSB V Bipolar operation
DAC Output Impedance 6.25 kΩ Tolerance typically 20%
Power Supply Rejection Ratio
±1.0
ΔV
DD
± 10%
Output Noise Spectral Density
11.8
DAC code = 0x840 (AD5512A) or
0x8400 (AD5542A), frequency = 1 kHz,
unipolar mode
Output Noise 0.134 μV p-p 0.1 Hz to 10 Hz
DAC REFERENCE INPUT
2
Reference Input Range 2.0 V
DD
V
Reference Input Resistance
3
9 kΩ Unipolar operation
7.5 kΩ Bipolar operation
Reference Input Capacitance 26 pF Code 0x0000
26 pF Code 0xFFFF
LOGIC INPUTS
Input Current ±1 μA
Input Low Voltage, V
INL
0.8 V V
DD
= 2.7 V to 5.5 V
Input High Voltage, V
INH
2.4 V V
DD
= 2.7 V to 5.5 V
Input Capacitance
2
10 pF
Hysteresis Voltage
2
0.15 V
POWER REQUIREMENTS
V
DD
2.7 5.5 V All digital inputs at 0 V, V
LOGIC
, or V
DD
I
DD
125 150 µA V
IH
= V
LOGIC
or V
DD
and V
IL
= GND
V
LOGIC
1.8 5.5 V
I
LOGIC
15 24 µA All digital inputs at 0 V, V
LOGIC
, or V
DD
Power Dissipation 0.625 0.825 mW
1
For 2.7 V ≤ V
LOGIC
≤ 5.5 V, temperatures are as follows: A, B versions −40°C to +85°C.
2
Guaranteed by design, not subject to production test.
3
Reference input resistance is code-dependent, minimum at 0x8555.
Data Sheet AD5512A/AD5542A
Rev. C | Page 5 of 21
AC CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V, V
LOGIC
= 2.7 V to 5.5 V, 2.5 V ≤ V
REF
≤ V
DD
, AGND = D G ND = 0 V, −40°C < T
A
< +125°C, unless otherwise noted.
Table 4.
Parameter Min Typ Max Unit Test Condition
Output Voltage Settling Time
1
μs
To 1/2 LSB of FS, C
L
= 10 pF
Slew Rate 17 V/µs C
L
= 10 pF, measured from 0% to 63%
Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around major carry
Reference −3 dB Bandwidth 2.2 MHz All 1s loaded
Reference Feedthrough 1 mV p-p All 0s loaded, V
REF
= 1 V p-p at 100 kHz
Digital Feedthrough 0.2 nV-sec
Signal-to-Noise Ratio
92
dB
Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz
Total Harmonic Distortion 74 dB
DAC code = 0x3FFF (AD5512A) or 0xFFFF (AD5542A), frequency 10 kHz,
V
REF
= 2.5 V ± 1 V p-p
AD5512A/AD5542A Data Sheet
Rev. C | Page 6 of 21
TIMING CHARACTERISTICS
V
DD
= 5 V, 2.5 V ≤ V
REF
≤ V
DD
, V
INH
= 90% of V
LOGIC
, V
INL
= 10% of V
LOGIC
, AGND = DGND = 0 V, unless otherwise noted.
Table 5.
Parameter
1, 2
Limit
1.8 ≤ V
LOGIC
≤ 2.7 V
3
Limit 2.7 V ≤ V
LOGIC
≤ 5.5 V
4
Unit Description
f
SCLK
14 50 MHz max SCLK cycle frequency
t
1
70 20 ns min SCLK cycle time
t
2
35 10 ns min SCLK high time
t
3
35 10 ns min SCLK low time
t
4
5 5 ns min
CS low to SCLK high setup
t
5
5 5 ns min
CS high to SCLK high setup
t
6
5 5 ns min
SCLK high to CS low hold time
t
7
10 5 ns min
SCLK high to CS high hold time
t
8
35
10
ns min
Data setup time
t
9
5
4
ns min
Data hold time (V
INH
= 90% of V
DD
, V
INL
= 10% of V
DD
)
t
9
5 5 ns min Data hold time (V
INH
= 3 V, V
INL
= 0 V)
t
10
20 20 ns min
LDAC pulsewidth
t
11
10
10
ns min
CS high to LDAC low setup
t
12
15 15 ns min
CS high time between active periods
t
13
15 15 ns
CLR pulsewidth
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
R
= t
F
= 1 ns/V and timed from a voltage level of (V
INL
+ V
INH
)/2.
3
−40°C < T
A
< +105°C.
4
−40°C < T
A
< +125°C.
SCLK
CS
DIN
DB15
1
DB11
2
LDAC
t
6
t
4
t
12
t
8
t
9
t
2
t
3
t
1
t
7
t
5
t
1
1
t
10
CLR
t
13
09199-003
NOTES
1. FOR AD5542A = DB15.
2. FOR AD5512A = DB11.
Figure 3. Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD5542ABCPZ-1-RL7

Mfr. #:
Buy AD5542ABCPZ-1-RL7
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16b 2LSB 2.7-5.5V w/ CLR Vlogic
Lifecycle:
New from this manufacturer.
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