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AD5542ABCPZ-1-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet AD5512A/AD5542A
Rev. C | Page 7 of 21
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 6.
Parameter Rating
V
DD
to AGND −0.3 V to +6 V
Digital Input Voltage to DGND
−0.3 V to V
DD
+ 0.3 V
V
OUT
to AGND −0.3 V to V
DD
+ 0.3 V
AGNDF, AGNDS to DGND −0.3 V to +0.3 V
Input Current to Any Pin Except Supplies ±10 mA
Operating Temperature Range
AD5512A Industrial (A Version)
−40°C to +125°C
AD5542A Industrial (A, B Versions) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature (T
J
max) 150°C
Package Power Dissipation (T
J
max − T
A
)/θ
JA
Thermal Impedance, θ
JA
TSSOP (RU-16)
113°C/W
LFCSP (CP-16-22)
73°C/W
LFCSP (CP-10-9)
74°C/W
Lead Temperature, Soldering
Peak Temperature
1
260°C
ESD
2
5 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
1
As per JEDEC Standard 20.
2
HBM classification.
AD5512A/AD5542A Data Sheet
Rev. C | Page 8 of 21
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
09199-036
12
11
10
1
3
4
DGND
LDAC
CLR
9
DIN
V
OUT
AGNDS
2
AGNDF
REFS
6
CS
5
REFF
7
NC
8
SCLK
16
R
FB
15
V
DD
14
V
LOGIC
13
INV
TOP
VIEW
(Not to
Scale)
AD5512A/AD5542A
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD SHOULD BE TIED
TO THE POINT OF LOWEST POTENTIAL,
IN THIS CASE, GND.
Figure 4. AD5512A/AD5542A 16-Lead LFCSP Pin Configuration
1REF
2CS
3SCLK
4DIN
5CLR
10 GND
9V
DD
8R
FB
7INV
6V
OUT
09199-034
AD5542A-1
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD SHOULD BE TIED
TO THE POINT OF LOWEST POTENTIAL,
IN THIS CASE, GND.
Figure 5. AD5542A-1 10-Lead LFCSP Pin Configuration
Table 7. AD5512A/AD5542A Pin Function Descriptions
Pin No.
16-Lead
LFCSP
10-Lead
LFCSP Mnemonic Description
1 6 V
OUT
Analog Output Voltage from the DAC.
2 AGNDF Ground Reference Point for Analog Circuitry (Force).
3 AGNDS Ground Reference Point for Analog Circuitry (Sense).
4 REFS
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to V
DD
.
5 REFF
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to V
DD
.
6 2
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
7 NC No Connect.
8 3 SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be
between 40% and 60%.
9 4 DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the
rising edge of SCLK.
10 5
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses
are ignored. When CLR
is activated, the DAC register is cleared to the model selectable midscale.
11
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the
contents of the input register.
12 DGND Digital Ground. Ground reference for digital circuitry.
13 7 INV
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op
amps inverting input in bipolar mode.
14 V
LOGIC
Logic Power Supply.
15 9 V
DD
Analog Supply Voltage, 5 V ± 10%.
16 8 R
FB
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
1 REF
Voltage Reference Input for the DAC. Connect this pin to an external 2.5 V reference. Reference can
range from 2 V to V
DD
.
10 GND Ground.
EPAD EPAD Exposed Pad The exposed pad should be tied to the point of lowest potential, in this case, GND.
Data Sheet AD5512A/AD5542A
Rev. C | Page 9 of 21
NC = NO CONNECT
1
2
3
4
5
6
7
8
V
OUT
AGNDF
AGNDS
NC
REFF
REFS
R
FB
CS
16
15
14
13
12
11
10
9
V
LOGIC
INV
DGND
DIN
SCLK
CLR
LDAC
V
DD
AD5542A
TOP VIEW
(Not to Scale)
09199-035
Figure 6. AD5542A 16-Lead TSSOP Pin Configuration
Table 8. AD5542A Pin Function Descriptions
Pin No.
Mnemonic
Description
1 R
FB
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
2
V
OUT
Analog Output Voltage from the DAC.
3 AGNDF Ground Reference Point for Analog Circuitry (Force).
4 AGNDS Ground Reference Point for Analog Circuitry (Sense).
5 REFS
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to V
DD
.
6 REFF
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to V
DD
.
7 NC No Connect.
8
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
9 SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
10 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
11
CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the DAC register is cleared to the model selectable midscale.
12
LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
13 DGND Digital Ground. Ground reference for digital circuitry.
14
INV
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting
input in bipolar mode.
15 V
LOGIC
Logic Power Supply.
16 V
DD
Analog Supply Voltage, 5 V ± 10%.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD5542ABCPZ-1-RL7

Mfr. #:
Buy AD5542ABCPZ-1-RL7
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16b 2LSB 2.7-5.5V w/ CLR Vlogic
Lifecycle:
New from this manufacturer.
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