© Semtech 2006 www.semtech.com
26
XE1202A TrueRF™
When “RTParam_Bits” is “0”, the bit synchronizer is turned off, and the signal DATAOUT is the output of the
demodulator. In this case DCLK is not used and its value is set to “low”. The maximum current drive on DATAOUT
and DCLK is 2 mA @ 2.7 V, the maximum load is CLop.
5.6 Pattern Recognition Interface
When this feature is enabled, the incoming NRZ bit stream is compared with a pattern stored in the “Pattern”
register. The PATTERN output (active-low) is driven by the output of this comparator and is synchronized by DCK.
It is asserted when a match is detected, otherwise negated (please see Figure 12, below). Changes occur at the
rising edge of DCK.
When the feature is disabled, the PATTERN output is always negated. The maximum current drive on PATTERN is
2 mA @ 2.7 V, the maximum load is CLop.
5.7 Clock Output Interface
CLKOUT is a clock signal at 1.22, 2.44, 4.87, or 9.75 MHz, depending on user-programming. When the XE1202A
TrueRF™ is in Sleep Mode (MODE[2:0] = 000) or when “RTParam_Clkout” is low, this clock is disabled.
5.8 Default settings at power-up
Upon power-up all RTParam, FSParam, ADParam and Pattern registers are set to 00H.
At power-up, the XE1202A TrueRF™ is in Standby mode, which means that the Xtal oscillator is enabled;
additionally a clock signal at 1.22 MHz (reference frequency divided by 32) is present at CLKOUT. However,
internally, RTParam_Clkout is low, which means that if the configuration register remains unaltered, the clock
signal at CLKOUT will be disabled on the first rising edge of /EN; in addition, at the first rising edge of /EN, the
circuit will be put in the mode corresponding to the status of the signals at MODE(2:0) inputs. Thus, to keep the
circuit in Standby mode and the clock signal present on CLKOUT, RTParam_Clkout has to be set high during the
first communication through the 3-wire bus, and the MODE(0) has to be set high before the first rising edge of /EN.
DATAOUT
(NRZ)
DCLK
BIT N
BIT N+1
DATAOUT
(NRZ)
DCLK
BIT N
BIT N+1
DATAOUT
(NRZ)
DCLK
BIT N=PATTERN[0]
PATTERN
BIT N-1=PATTERN[1]BIT N - x=PATTERN[x]
DATAOUT
(NRZ)
DCLK
BIT N=PATTERN[0]
PATTERN
BIT N-1=PATTERN[1]BIT N - x=PATTERN[x]
Figure 11: DATAOUT timing
Figure 12: Pattern Recognition timing
