1©2016 Integrated Device Technology, Inc January 6, 2016
General Description
The 843S304I-100 is a PLL-based clock generator specifically
designed for low phase noise applications. This device generates a
100MHz differential LVPECL clock from a input reference of 25MHz.
The input reference may be derived from an external source or by
the addition of a 25MHz crystal to the on-chip crystal oscillator. An
external reference is applied to the PCLK pins.
The nominal output frequency of 100MHz may be margined by
approximately ±5% by changing the M divider value via the I
2
C
interface.
The device offers spread spectrum clock output for reduced EMI
applications. An I
2
C bus interface is used to enable or disable spread
spectrum operation as well as set the amount of spread. The
843S304I-100 is available in a lead-free 32-Lead VFQFN package.
Features
Four LVPECL output pairs
Crystal oscillator interface: 25MHz
Output frequency: 100MHz
PCI Express Gen 2 (5 Gb/s) Jitter compliant
RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.01ps (typical)
I
2
C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
HiPerClockS™
Divider
Network
PLL
OSC
I
2
C
Logic
Q[1:4]
nQ[1:4]
Pullup
Pullup
Pullup/Pulldown
Pulldown
Pulldown
XTAL_IN
XTAL_OUT
S DATA
Pulldown
ADR
PCLK
nPCLK
REF_SEL
SCLK
25MHz
1
0
Pulldown
nCLK_EN
4
4
843S304I-100
32-Lead VFQFN
5.0mm x 5.0mm x 0.925mm
package body
K Package
Top View
Pin Assignment
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
REF_SEL
V
EE
PCLK
nPCLK
V
EE
VCCA
nCLK_EN
V
EE
nQ3
Q3
V
CC
VEE
nQ4
Q4
V
CC
VCC
VEE
VCC_XOSC
XTAL_IN
XTAL_OUT
ADR
SCLK
SDATA
nQ1
Q1
V
CC
VCC
nQ2
Q2
V
CC
VEE
Block Diagram
Crystal-to-LVPECL 100MHz Clock
Synthesizer
843S304I-100
Data Sheet
2©2016 Integrated Device Technology, Inc January 6, 2016
843S304I-100 Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 9, 17,
21, 25, 28, 29
V
CC
Power Core supply pins.
2 REF_SEL Input Pullup
Select input for XTAL (LOW) or PCLK (HIGH).
LVCMOS/LVTTL interface levels.
3, 6,10,
20, 24, 32
V
EE
Power Negative supply pins.
4 PCLK Input Pulldown External 25MHz non-inverted differential reference input. LVPECL input levels.
5 nPCLK Input
Pullup/
Pulldown
External 25MHz inverted differential reference input. V
CC
/2 bias voltage when left
floating. LVPECL input levels.
7V
CCA
Power Analog supply for PLL.
8 nCLK_EN Input Pulldown
Places clock outputs in active state when Low. Places clock outputs in
high-impedance state when High.
11 V
CC_XOSC
Power Power supply for crystal oscillator. recommended to use RC filter as on V
CCA
.
12,
13
XTAL_IN,
XTAL_OUT
Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
14 ADR Input Pulldown I
2
C Address select pin. LVCMOS/LVTTL interface levels.
15 SCLK Input Pullup
I
2
C compatible SCLK. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
16 SDATA I/O Pullup
I
2
C compatible SDATA. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
18,19 Q4, nQ4 Output Differential output pair. LVPECL interface levels.
22, 23 Q3, nQ3 Output Differential output pair. LVPECL interface levels.
26, 27 Q2, nQ2 Output Differential output pair. LVPECL interface levels.
30, 31 Q1, nQ1 Output Differential output pair. LVPECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
3©2016 Integrated Device Technology, Inc January 6, 2016
843S304I-100 Data Sheet
I
2
C Interface - Protocol
The 843S304I-100 uses an I
2
C slave interface for writing
configuration values and reading PLL status bits to and from the
on-chip configuration and status registers. This device uses the
standard I
2
C write format for a write transaction, and a standard I
2
C
combined format for a read transaction. Figure 1 defines the I
2
C
elements of the standard I
2
C transaction. These elements consist of
a Start bit, Data bytes, an Acknowledge or Not-Acknowledge bit and
the Stop bit. These elements are arranged to make up the complete
I
2
C transactions as shown in Figures 2A and 2B. Figure 2A is a write
transaction while Figure 2B is the combined transaction as used for
the read. Please refer to the I
2
C Bus Specification for a detailed
explanation on I
2
C operation.
Figure 1. Standard I
2
C Transaction
START (ST) - defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA - Between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (AK) - SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
STOP (SP) - defined as low-to-high transition on SDA while holding
SCL HIGH.
S Start or Repeated Start DevAdd 7 bit Slave Address
The 843S304I-100 also uses an additional register address byte to
ensure valid I
2
C transactions to the device registers. The byte
contains the 1’s complement of the slave address. This additional
address byte is referred to as the Secure I
2
C interface. This Secure
I
2
C interface can be accessed by most software driver routines that
handle standard I
2
C transactions.
SCL
SDA
START
Valid Data
Acknowledge
STOP
SWAAAAPDevAdd RegAdd ~RegAdd Data
SWA A ASRA APDevAdd RegAdd ~RegAdd DevAdd
Data
Master-to-Slave
Slave-to-Master
Figure 2A. Write Transaction
Figure 2B. Combined Transaction (Read)

843S304BKI-100LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Crystal-to-LVPECL 133MHz Clock Synth
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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