843S304BKI-100LFT Datasheet 843S304BKI-100LFT, 843S304BKI-100LF | P4-P6

843S304I-100 Data Sheet

SECURE I

C Interface Communication

C Write Transaction

An I

C communication write transaction to the 843S304I-100 is

initiated by the I

C master sending a start bit. A start bit is a

high-to-low transition on the serial data (SDA) input/output line while

the serial clock (SCL) input is high. After the start condition, the 7 bit

C slave-address is sent, MSB first, followed by the read/~write bit.

The read/~write bit is set low to indicate a write operation. After

receiving the valid I

C slave-address, the slave device,

843S304I-100 responds with an acknowledge (ACK). Next, the

master sends the 8 bit register address that is to be accessed by this

transaction. Again the 843S304I-100 responds with an acknowledge

bit. The master then sends the one’s complement of the 8 bit

sends the 8 bit data value to be stored in the previously addressed

will issue a stop.

C Read Transaction

A read operation uses the I

C Combined Transaction. The combined

transaction has a direction change from a write to a read in the

middle of the transaction, allowing a register address to be sent to

the 843S304I-100 and data to be received from the slave device. As

with a write, the combined transaction starts with the master sending

a start condition and is then followed by the 7 bit slave address, and

then followed by the R/~W bit being set for a write. This slave, if

properly addressed, will respond with an Acknowledge (A). Next, as

with the write transaction, the master sends the 8 bit register

address that is to be accessed by this transaction. Once again this

device would respond with an acknowledge. The master then sends

the one’s complement of the 8 bit register address with an

acknowledgment from the slave. The master will next send a

repeated start bit followed by the slave address and the R/~W bit set

to a one which is for a read operation. The 843S304I-100 will

acknowledge and then proceed to send the data byte associated

with the previously addressed register. The master will acknowledge

and then send a stop bit indicating the end of the transaction.

SYNTHESIZER CONFIGURATION AND I

C PROGRAMMING REGISTERS

The 843S304I-100 uses the Secure I

C interface to configure the

internal dividers of the PLL. The Secure I

C interface allows the

change of the M dividers, and additionally, may be used to turn on,

select the amount, and select the direction of spread spectrum

modulation through a series of read/write 8 bit registers. Table 3

shows the registers, their address, and description of each of the

bits in the registers. Some of the bits in these registers are not

defined and are ignored on writes and will read-back as zeros on an

C read transaction. Note, the Command register, which will be

described below is a write only register, and an attempted read of

this register will result in a NACK or not-acknowledge being returned

to the I

C master.

Table 3. Register Table

00 Command Register 1 nCL nST nCP 0 CL ST CP

01 Lower M Dividers

M4 M3 M2 M1 M0 N/A N/A N/A

02 Upper M Dividers

N/A N/A M10 M9 M8 M7 M6 M5

03 Spread Spectrum Control N/A UP DN SS4 SS3 SS2 SS1 SS0

04 Status Read Only N/A N/A N/A N/A N/A N/A N/A N/A

843S304I-100 Data Sheet

The 843S304I-100 can be set to decode on of two device I

C slave

addresses to minimize the chance of address conflicts on the I

bus. The specific address that is decoded by the 843S304I-100 is

controlled by the setting of the ADR input (pin 14). This input pin

determines the value of the I

C address bit A1. See Table 4 for the

slave addresses for the 843S304I-100.

Table 4. I

C Slave Address Table

Writing to and Reading from the Secure I

C Interface

Data is communicated to and from the 843S304I-100 registers using

the secure I

C interface. The data is read from or written to a

command register and a staging register as shown in Figure 3. This

diagram shows the relative location of the Command Register, the

Staging Register and the Main Register. The main register directly

controls the actual PLL operation whose contents is only available

through the Staging and Command registers.

The 8 bit command register (address 00) consists of three command

bits in the lower nibble and the 1’s compliment of those three

command bits in the upper nibble. The setting of one of the bits in

the lower nibble and the clearing of the 1’s complement bit in the

upper nibble is used to command either a copy from the Main

to the Main Register, or a Clear of an error flag or flags. All I

C writes

to the command register must contain the bitwise compliment of the

three lower bits in the three upper bits or the write will be ignored

and a NACK will be returned from the 843S304I-100. For example

the valid command for the Copy is 1110 0001.

To read the contents of the main register, a command should be sent

to copy the contents of the Main register to the Staging register. This

command is sent by setting bit D0 (CP) and clearing bit D4 (nCP)

with an I

C write of 1110 0001 into the command register (register

00). After this command is sent, the contents of the main register is

copied from the Main register to the Staging register and then the

resultant data can be read out by the secure I

C interface without

affecting the operation of the synthesizer. The data is read by an I

read transaction to register 01, register 02, register 03 or register 04.

A multi-byte read may be performed by using the I

C specified

transaction.

In order to store data to the Main register, the data must first be

written to the Staging register associated with the desired register

address. Following the I

C write into the Staging register, the data

can be verified, if desired, by reading back the Staging register with

an I

C read transaction. The contents in the Staging register can

then be stored into the Main register with a Store command. The

Store command is sent by setting bit D1 (ST) and clearing bit D5

(nST) with an I

C write of 1101 0010 into register 00 or the command

the operation of the synthesizer. A multibyte write to the staging

registers may be done with a multibyte I

C write transaction. The

the I

C transaction will represent the beginning address for the write.

The 843S304I-100 will automatically increment the register address

such that the multiple bytes are stored in successive register

locations.

Figure 3. Writing to and Reading from the Secure I

C Interface

Bit A7A6A5A4A3A2A1A0

ADR = 0 (default)1011000R/W

ADR = 1 1011001R/W

Staging Register

Command

Main Register

Store

SCL

SDA

Copy

843S304I-100 Data Sheet

SPREAD SPECTRUM OPERATION

Spread Spectrum operation is controlled by I

C register 03, Spread

Spectrum Control Register. Bits D0 – D4 (SS) of the register are a

subtrahend to the M-divider for down-spread, and they are an

addend and a subtrahend to the M-divider for center-spread. When

the UP bit is HIGH, then up-spread has been selected and the

M-divider value will toggle between the programmed M value, and

M+SS at a 32kHz rate. When the DN bit is HIGH, then down- spread

has been selected and the M-divider value will toggle between the

programmed M value, and M-SS at a 32kHz rate. When both the UP

and DN bits are HIGH, then center-spread has been selected and

the M-divider will toggle between M+SS and M-SS at a 32kHz rate.

To disable Spread Spectrum operation, program both the UP and

DN bits to LOW.

Programmable Output Frequency Operation

The M value and the required values of M0 through M10 are shown

in Table 5 to program the VCO Frequency Function Table. Valid M

values for which the PLL will achieve lock for a 25MHz reference are

defined as 91 M 101. The frequency out is defined as follows:

OUT

= f

VCO

/N = f

XTAL

x M/N

For the 843S304I-100 N = 24.

Table 5. Programmable VCO Frequency Function Table

PLL BYPASS

The device will be placed into PLL bypass mode when all the M bits

are set to zeros.

VCO

Frequency

(MHz) M Divide

Output

Frequency

(MHz)

1024 512 256 128 64 32 16 8 4 2 1

M10 M9 M8M7M6M5M4M3M2M1M0

2275 91 94.792 0 0 0 0 1 0 1 1 0 1 1

2300 92 95.833 0 0 0 0 1 0 1 1 1 0 0

••• ••••••••••

2375 95 98.958 0 0 0 0 1 0 1 1 1 1 1

2400

(default)

100 0 0 0 0 1 1 0 0 0 0 0

2425 97 101.042 0 0 0 0 1 1 0 0 0 0 1

••• ••••••••••

2500 100 104.167 0 0 0 0 1 1 0 0 1 0 0

2525 101 105.208 0 0 0 0 1 1 0 0 1 0 1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

843S304BKI-100LFT

Mfr. #:

Buy 843S304BKI-100LFT

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner Crystal-to-LVPECL 133MHz Clock Synth

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New from this manufacturer.

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843S304BKI-100LFT

843S304BKI-100LFT

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