16©2016 Integrated Device Technology, Inc January 6, 2016
843S304I-100 Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 9. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 9. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
17©2016 Integrated Device Technology, Inc January 6, 2016
843S304I-100 Data Sheet
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The below block diagram shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well
as the phase interpolator in the receiver. These transfer functions
are called H1, H2, and H3 respectively. The overall system transfer
function at the receiver is:
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is
reported in peak-peak. For PCI Express Gen 2, two transfer
functions are defined with 2 evaluation ranges and the final jitter
number is reported in rms. The two evaluation ranges for PCI
Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz -
Nyquist (High Band). The below plots show the individual transfer
functions as well as the overall transfer function Ht. The respective
-3 dB pole frequencies for each transfer function are labeled as F1
for transfer function H1, F2 for H2, and F3 for H3. For a more
thorough overview of PCI Express jitter analysis methodology,
please refer to IDT Application Note PCI Express Reference Clock
Requirements.
Ht s H3 s H1 s H2 s=
Ys Xs H3 s H1 s H2 s=
18©2016 Integrated Device Technology, Inc January 6, 2016
843S304I-100 Data Sheet
PCIe Gen 1 Magnitude of Transfer Function
PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function
10
3
10
4
10
5
10
6
10
7
-60
-50
-40
-30
-20
-10
0
Frequency (Hz)
Mag (dB)
Magnitude of Transfer Functions - PCIe Gen 1
F1: 2.2e+007 F2: 1.5e+006
F3: 1.5e+006
H1
H2
H3
Ht=(H1-H2)*H3
10
3
10
4
10
5
10
6
10
7
-60
-50
-40
-30
-20
-10
0
Frequency (Hz)
Mag (dB)
Magnitude of Transfer Functions - PCIe Gen 2A
F1: 1.6e+007 F2: 5.0e+006
F3: 1.0e+006
H1
H2
H3
Ht=(H1-H2)*H3
10
3
10
4
10
5
10
6
10
7
-60
-50
-40
-30
-20
-10
0
Frequency (Hz)
Mag (dB)
Magnitude of Transfer Functions - PCIe Gen 2B
F1: 1.6e+007 F2: 8.0e+006
F3: 1.0e+006
H1
H2
H3
Ht=(H1-H2)*H3

843S304BKI-100LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Crystal-to-LVPECL 133MHz Clock Synth
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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