10©2016 Integrated Device Technology, Inc January 6, 2016
843S304I-100 Data Sheet
Typical Phase Noise
100MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.01ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
11©2016 Integrated Device Technology, Inc January 6, 2016
843S304I-100 Data Sheet
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
Differential Input Level
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
V
CC
2V
-1.3V± 0.165V
2V
V
CCA
V
CC_XOSC
nQ[1:4]
Q[1:4]
V
CC
V
EE
V
CMR
Cross Points
V
PP
nPCLK
PCLK
nQ[1:4]
Q[1:4]
12©2016 Integrated Device Technology, Inc January 6, 2016
843S304I-100 Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 843S304I-100 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V
CC ,
V
CC_XOSC
and V
CCA
should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 4
illustrates this for a generic V
CC
pin and also shows that V
CCA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V
CCA
pin.
Figure 4. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied
from XTAL_IN to ground.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from PCLK to
ground.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
V
CC
V
CCA
V
CC_XOSC
3.3V
10Ω
10Ω
10µF.01µF
.01µF
10µF.01µF

843S304BKI-100LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Crystal-to-LVPECL 133MHz Clock Synth
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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