LTC4226
18
4226f
Figure 11. Recommended Layout
Design Example
As a design example, take the following specifications for
Figure 8 with a load capacitor C
OUT
of 1mF (not shown on
schematic) at the cable end of port 1:
The channel is rated for a maximum V
CC
of 33V at 1.5A,
C
OUT
= 1mF and current limit at 1.5× of circuit breaker
current.
Circuit breaker current plus a 15% margin:
I
CB
= 1.5A • 1.15 = 1.725A,
Sense resistor:
R
S
=
50mV
1.5A • 1.15
≈ 29mΩ
Start-up in current limit with CLS low,
V
LIMIT
= 1.5 • 1.15 • V
CB
and
I
LIMIT
= 1.5 • 1.15 • I
CB
≈ 2.98A
Calculate the time it takes to charge up C
OUT
in current limit:
t
CHARGE
=
C
OUT
• V
CC
I
LIMIT
≈ 11ms
During a normal start-up where all of the current charges
C
OUT
, the average power dissipation in the MOSFET is
given by:
P
DISS
=
V
CC
•I
LIMIT
= 49.2W
If the output is shorted to ground, the average power
dissipation in MOSFET doubles:
P
DISS
= V
CC
• I
LIMIT
= 98.4W
The SOA (safe operating area) curve for the FDMS86500DC
MOSFET shows 100W for 35ms. During a normal start-
up the MOSFET dissipates 49.2W for 11ms at 33V with
adequate SOA margin.
Setting the current limit fault timeout at about 14ms gives:
C
T
=
t
LIMIT
• 20µA
1.23V
= 228nF
Choose a standard value of 220nF. The resulting FTMR
timeout in current limit is:
t
LIMIT
= 13.5ms
The FTMR circuit breaker timeout is:
t
CB
= 135ms
The resistor pair R1 and R2 sets the ON threshold voltage
for both channels. In this case R1 = 150k, R2 = 50k:
V
CC
ON Threshold=
R1+R2
• 1.23
= 4.92V
Layout Considerations
To achieve accurate current sensing, Kelvin connections
for the sense resistor are recommended. The PCB layout
of Kelvin sensing traces should be balanced, symmetrical
and minimized to reduce error. In addition, the PCB layout
for the sense resistors and the power MOSFETs should
include good thermal management techniques for device
power dissipation such as vias and wide metal area. A
recommended PCB layout for the sense resistor and power
MOSFET is illustrated in Figure 11. To avoid the need for
the additional MOSFET GATE pin resistor (R1 in Figure 13),
the GATE trace over ground plane should have minimized
trace length and capacitance.
applicaTions inForMaTion
G2
R
S2
4226 F11
R
G1
1
R
S1
Q1
LTC4226
