LTC4226
9
4226f
operaTion
The LTC4226 controls two independent Hot Swap channels.
It is designed to turn each supply voltage on and off in a
controlled manner, allowing live insertion into a powered
connector or backplane.
The LTC4226 powers-up the output of a channel when that
channel’s V
CC
pin has remained above the 3.7V undervolt-
age lockout threshold V
CC(UVL)
for more than 50ms and
its ON pin has remained above the V
ON
threshold for more
than 10ms. During normal operation, a charge pump turns
on the external N-channel MOSFET providing power to
the load. Each channel’s charge pump derives its power
from its own V
CC
supply pin. To protect the MOSFET, the
GATE voltage is clamped at about 12V above the OUT pin.
It is also clamped a diode voltage below the OUT pin and
a diode voltage below GND.
The current flowing through the MOSFET is measured by
the external sense resistor. The sense voltage across the
sense resistor is measured between the V
CC
and SENSE
pins. The LTC4226 has a circuit breaker (CB) comparator
to detect the sense current above circuit breaker thresh-
old and a current limit (CL) amplifier to actively
clamp
the sense current at the current limit threshold. Both the
CB comparator and the CL amplifier monitor the sense
resistor voltage between the V
CC
and SENSE pins. When
the sense voltage exceeds V
CB
but is below V
LIMIT
, the
CB comparator enables a 2μA I
FTMR(CB)
current source
that ramps up the voltage on the FTMR pin. If the sense
resistor voltage exceeds V
LIMIT
, the CL amplifier limits
the current in the MOSFET by reducing the GATE-to-OUT
voltage with an active control loop. The fast response CL
amplifier can quickly gain control of the GATE-to-OUT
voltage in the event of an OUT-to-GND short circuit. The
FTMR pin is ramped up by the larger I
FTMR(CL)
current
source during active current limiting. If the sense voltage
falls below V
CB
, the FTMR is ramped down by the default
2μA I
FTMR(DEF)
pull-down current.
A fault timeout occurs when an overcurrent condition
persists above V
CB
that causes the FTMR pin to ramp to
the V
FTMR(H)
threshold. When this occurs, the MOSFET
is turned off and the FAULT pin asserts low. The FTMR
has two timeout durations: a
longer circuit breaker (CB)
timeout
with a lower current I
FTMR(CB)
ramp up when the
current limit is not activated and a shorter current limit
(CL) timeout with a higher current I
FTMR(CL)
ramp up if
current limit is active. The CLS input state sets the higher
current I
FTMR(CL)
at 20μA when CLS = 0V; 36μA when
CLS = open; 80μA when CLS > 2V.
During current limit, the sense voltage is at V
LIMIT
. There
can be significant MOSFET power dissipation while in cur-
rent limit due to the substantial drain-to-source voltage.
The CL timeout duration should be selected based on the
external MOSFET safe-operating-area to prevent MOSFET
damage. The CL timeout is set by the FTMR capacitor C
T
and the I
FTMR(CL)
pull-up to the V
FTMR(H)
threshold. Setting
the current limit higher than the circuit breaker threshold
allows momentary current load spikes as long as the
average current remains below the circuit breaker limit.
Both channels share a common current limit select, CLS
pin. This pin has three input states: low, open and high.
The three input states configure the preset current limit
V
LIMIT
to approximately 1.5×, 2× or 3× of 1.15 • V
CB
.
After a fault timeout, the auto-retry (LTC4266-2) version
waits 0.5 seconds before resetting FTMR. After the FTMR
capacitor is discharged, the GATE pin is free to ramp up
again after the FAULT pin resets high. For the latchoff
(LTC4266-1) version, there is no 0.5 second restart delay.
For both versions, FTMR can be reset by cycling the ON
pin low and then high or by cycling V
CC
below and then
above UVLO.
The FAULT pin pulls low when active with a 5mA current
limit. The pin can drive a low-current 2mA LED with a
series resistor connected to V
CC
. The FAULT pin has an
internal 10μA pull-up current to a diode below its internal
V
CC
when signaling no fault. Pulling the FAULT pin below
the V
FAULT
threshold causes the external MOSFET to turn
off without affecting FTMR status. The FAULT pin can be
wire-OR’ed with other open-drain outputs.
The output voltage of the Hot Swap circuit is ramped
down when the ON pin transitions low or V
CC
falls below
the 3.7V undervoltage lockout. The gate driver discharges
the GATE pin with 3mA (including 2.85mA to the OUT pin
)
when
GATE > OUT and 150µA to GND when GATE < OUT.
