LTC4226
19
4226f
In Hot Swap applications where load currents can be 5A,
narrow PCB tracks exhibit more resistances than wide
tracks and operate at elevated temperatures. The mini-
mum trace width for 1oz copper foil is 0.02" per amp to
make sure the trace stays at a reasonable temperature.
Using 0.03" per amp or wider is recommended. Note that
1oz copper exhibits a sheet resistance of about 0.5mΩ/
square. The use of vias allow multi-copper planes to be
used to improve both electrical conduction and thermal
dissipation. Thicker top and bottom copper such as 3oz
or more can improve electrical conduction and reduce
PCB trace dissipation.
It is important to minimize noise pickup on PCB traces
for ON, FTMR, FAULT, CLS and GATE. If an R
G
resistor is
used, place the resistor as close to the MOSFET gate as
possible to limit the parasitic trace capacitance that leads
to MOSFET self-oscillation.
Bidirectional Current Limiting
Figure 16 shows an application with bidirectional current
limiting with a common sense resistor. Figure 12 shows
an asymmetric bidirectional current limiter for operating
voltage between 7V and 30V using two separate sense
applicaTions inForMaTion
resistors. Separate resistors allow different current limit
in each direction to be set. The transient suppressor at the
sense
pins allow the circuit breaker to trip when either the
input or output voltage exceeds the suppressor breakdown
voltage. When the OUT voltage exceeds the suppressor
breakdown, GATE2 shuts down after FTMR2 time-out and
this can prevent suppressor blow out. The timing capacitor
at FTMR2 can be selected to keep the suppressor within
safe operating area.
High Current Applications
Figure 13 and Figure 14 show 44A and 89A continuous
current applications for bus power distribution. The bus
connection inductance causes a supply dip at the sense
resistor when there is a load transient. The worst transient
is a short at the output or the sudden connection of an
uncharged load capacitor. Without capacitors C1 and C2
for channel 1, V
CC1
voltage can dip below the LTC4226
undervoltage lockout threshold resulting in a channel 1
UVLO reset. The low ESR electrolytic capacitor C1 and
ceramic capacitor C2 should be placed very close to the
sense resistor V
CC1
terminal and the ground plane to
minimize inductance.
Figure 12. 7V to 30V Asymmetric Bidirectional Current-Limiter
SMCJ33A
FTMR1
GND
220nF
50mΩ
FDMS86500DC
OR Si7164DP
220nF
FTMR2
ON1
SENSE2 V
CC2
GATE1
LTC4226-2
OUT1
FAULT1
CLS
FAULT2
ON2
FAULT1
CLS
FAULT2
30mΩ
V
CC1
SENSE1
FDMS86500DC
OR Si7164DP
GATE2
OUT2
OUT
7V TO 30V RANGE
1.48A/0.89A
V
IN
7V TO 30V RANGE
4226 F12
