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SSTUB32866BHLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
10
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
‡
CK
D1•D25
†
RST
t
su
t
pd
CK to PPO
t
h
t
su
t
h
t
pdm
, t
pdmss
CK to Q
DCS
CSR
CK
Q1•Q25
PAR_IN
†
nn + 1n + 2
PPO
n + 3 n + 4
t
PHL
CK to QERR
QERR
‡
t
PHL
, t
PLH
CK to QERR
t
act
H, L, or X H or L
Data to QERR Latency
After RST is switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error.
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
ACT
Figure 9 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST Switches from L to H
11
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
CK
D1•D25
RST
t
su
t
pd
CK to PPO
t
h
t
su
t
h
t
pdm
, t
pdmss
CK to
DCS
CSR
CK
Q1•Q25
PAR_IN
n n + 1 n + 2
PPO
n + 3 n + 4
QERR
†
t
PHL
or t
PLH
CK to QERR
Unknown input
event
H or L
Output signal is dependent on
the prior unknown input event
Data to PPO Latency
Data to QERR Latency
Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST being held high
Figure 10
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RST is driven low.
12
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
CK
†
D1•D25
†
RST
DCS
†
CSR
†
CK
†
Q1•Q25
PAR_IN
†
PPO
QERR
t
inact
t
RPHL
RST to Q
t
RPHL
RST to PPO
t
RPLH
RST to QERR
H, L, or X H or L
Figure 11 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST switches from H to L
After RST is switched from high to low, all data and clock unouts signals must be set and held at valid logic levels (not floating) for
a minimum time of t max.
INACT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

SSTUB32866BHLF

Mfr. #:
Buy SSTUB32866BHLF
Manufacturer:
IDT
Description:
Clock Buffer 1.8V Reg. Buffer (800 MHz)
Lifecycle:
New from this manufacturer.
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