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SSTUB32866BHLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
25
ICSSSTUB32866B
Advance Information
1165A—3/21/07
CL =10pF
(1)
RL =1KΩ
DUT
Out
Test Point
V
DD
VOH
VCC
Output
Waveform 2
LVCMOS
RESET#
t
PLH
VCC/2
0.15V
0V
0V
VOH
Output
Waveform 2
0.15V
0V
VICR
tHL
VICR
VI(PP)
Timing Inputs
V
CC
VICR
tHL
Timing Inputs VICR
VI(PP)
Output
Waveform 1
V
CC/2
VOL
Load Circuit, error output measurements
Voltage Waveforms, open-drain output LOW-to-HIGH with respect to RESET# input
Voltage Waveforms, open-drain output HIGH-to-LOW with respect to clock inputs
Voltage Waveforms, open-drain output LOW-to-HIGH with respect to clock inputs
Notes: 1. C
L
includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Z
O
=
50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
26
ICSSSTUB32866B
Advance Information
1165A—3/21/07
CL =5pF
(1)
RL =1KΩ
DUT
Out
Test Point
VTT
VICR
tHL
VI(PP)
Output
V
TT
CLK
CLK
VICR
tHL
Partial parity out load circuit
Partial parity out voltage waveform, propagation
delay time with respect to CLK input
VTT =VDD/2
V
I(P-P) = 600mV
t
PLH and tPHL are the same as tPD
VTT =VDD/2
t
PLH and tPHL are the same as tPD
VIH =VREF + 250mV (AC voltage levels) for differential inputs. VIH =VDD for LVCMOS inputs.
V
IL =VREF - 250mV (AC voltage levels) for differential inputs. VIL =VDD for LVCMOS inputs.
V
IH
Output
V
DD/2
Input
LVCMOS RESET
VIL
VOH
VOL
VTT
tPHL
Partial parity out voltage waveform, propagation
delay time with respect to RESET input
27
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Ordering Information
ICSSSTUB32866Bz(LF)T
D E T e HORIZ VERT TOTAL d h b c
Min/Max Min/Max Min/Max
13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 0.25/0.41 0.75 0.75
11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 0.25/0.35 0.875 0.875
MO-205
10-0055C
* Source Ref.: JEDEC Publication 95,
ALL DIMENSIONS IN MILLIMETERS
REF. DIMENSIONS ----- BALL GRID ----- Max.
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
Example:
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
H = LFBGA (standard size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y z (LF) T
SEATING
PLANE
0.12
C
C
A
B
C
D
A1
D
E
TOP VIEW
T
hTYP
dTYP
4321
Numeric Designations
for Horizontal Grid
bREF
cREF
TYP
-e-
TYP
-e-
D1
E1
Alpha Designations
for Vertical Grid
(Letters I, O, Q, and
S not used)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

SSTUB32866BHLF

Mfr. #:
Buy SSTUB32866BHLF
Manufacturer:
IDT
Description:
Clock Buffer 1.8V Reg. Buffer (800 MHz)
Lifecycle:
New from this manufacturer.
Delivery:
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