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SSTUB32866BHLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
13
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
CK
D1•D14
†
RST
t
su
t
pd
CK to PPO
t
h
t
su
t
h
t
pdm
, t
pdmss
CK to Q
DCS
CSR
CK
Q1•Q14
PAR_IN
†
n n + 1 n + 2
PPO
n + 3 n + 4
t
PHL
CK to QERR
QERR#
‡
(not used)
t
PHL
, t
PLH
CK to QERR
t
act
H, L, or X H or L
Data to QERR#
Latency
Figure 12 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST switches from L to H
After RST is switched from low to high, all data and PAIR_IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse.
ACT
†
‡
14
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
CK
D1•D14
RST
t
su
t
pd
CK to PPO
t
h
t
su
t
h
t
pdm
, t
pdmss
CK to Q
DCS
CSR
CK
Q1•Q14
PAR_IN
n n + 1 n + 2
PPO
n + 3 n + 4
QERR
†
(not used)
t
PHL
or t
PLH
CK to QERR
Unknown input
event
H or L
Output signal is dependent on
the prior unknown input event
Data to QERR
Latency
Data to PPO
Latency
Figure 13 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST being held high
If the data is clocked in on the clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RST is driven low.
15
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
from high to low, all data and clock inputs signals must be held at valid logic levels (not floating) for a
minimum time of t
INACT
max
CK
†
D1•D14
†
RST#
DCS#
†
CSR#
†
CK#
†
Q1•Q14
PAR_IN
†
PPO
QERR#
(not used)
t
inact
t
RPHL
RST# to Q
t
RPHL
RST# to PPO
t
RPLH
RST# to QERR#
H, L, or X
H or L
After
is switchedRST#
Figure 14 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST# switches from H to L
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

SSTUB32866BHLF

Mfr. #:
Buy SSTUB32866BHLF
Manufacturer:
IDT
Description:
Clock Buffer 1.8V Reg. Buffer (800 MHz)
Lifecycle:
New from this manufacturer.
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