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SSTUB32866BHLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
16
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
‡ PAR_IN is driven from PPO of the first SSTU32866 device.
§ If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
CK
D1•D14
†
RST#
t
su
t
pd
CK to PPO
t
h
t
su
t
h
t
pdm
, t
pdmss
CK to Q
DCS#
CSR#
CK#
Q1•Q14
PAR_IN
†‡
n n + 1 n + 2
PPO
(not used)
n + 3 n + 4
t
PHL
CK to QERR#
QERR#
§
t
PHL
, t
PLH
CK to QERR#
t
act
H, L, or X
H or L
Data to QERR# Latency
Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in
pair; C0=1, C1=1; RST# switches from L to H
After RST# switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error.
ACT
†
17
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
18
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
CK
†
D1•D14
†
RST#
DCS#
†
CSR#
†
CK#
†
Q1•Q14
PAR_IN
†
PPO
(not used)
QERR#
t
inact
t
RPHL
RST# to Q
t
RPHL
RST# to PPO
t
RPLH
RST# to QERR#
H, L, or X H or L
†
Figure 17 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used i
n
pair; C0=1, C1=1; RST# switches from H to L
After RST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a
munimum time of t max.
INACT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

SSTUB32866BHLF

Mfr. #:
Buy SSTUB32866BHLF
Manufacturer:
IDT
Description:
Clock Buffer 1.8V Reg. Buffer (800 MHz)
Lifecycle:
New from this manufacturer.
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