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0334G–FLASH–2/05
AT29LV040A
the first data byte has been loaded into the device, successive bytes are entered in the same
manner. Each new byte to be programmed must have its high-to-low transition on WE
(or CE)
within 150 µs of the low-to-high transition of WE
(or CE) of the preceding byte. If a high-to-low
transition is not detected within 150 µs of the last low-to-high transition, the load period will end
and the internal programming period will start. A8 to A18 specify the sector address. The sector
address must be valid during each high-to-low transition of WE
(or CE). A0 to A7 specify the
byte address within the sector. The bytes may be loaded in any order; sequential loading is not
required. Once a programming operation has been initiated, and for the duration of t
WC
, a read
operation will effectively be a polling operation.
4.3 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29LV040A in the following
ways: (a) V
CC
sense – if V
CC
is below 1.8V (typical), the program function is inhibited; (b) V
CC
power on delay – once V
CC
has reached the V
CC
sense level, the device will automatically time
out 10 ms (typical) before programming; (c) Program inhibit – holding any one of OE
low, CE
high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical)
on the WE
or CE inputs will not initiate a program cycle.
4.4 Input Levels
While operating with a 3.3V ±10% power supply, the address inputs and control inputs (OE, CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.
The I/O lines can only be driven from 0 to 3.6V.
4.5 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product. In
addition, users may wish to use the software product identification mode to identify the part (i.e.,
using the device code), and have the system software use the appropriate sector size for pro-
gram operations. In this manner, the user can have a common board design for 256K to 4-
megabit densities and, with each density’s sector size in a memory map, have the system soft-
ware apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.6 DATA Polling
The AT29LV040A features DATA polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will result in the complement of the loaded
data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and
the next cycle may begin. DATA
polling may begin at any time during the program cycle.
4.7 Toggle Bit
In addition to DATA polling the AT29LV040A provides another method for determining the end
of a program or erase cycle. During a program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle.
