71V65603S100PFG Datasheet 71V65603S133BQG, 71V65603S100BQG, 71V65603S100PFG8 | P1-P3

OCTOBER 2008

DSC-5304/08

Pin Description Summary

Description

The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBT

, or Zero Bus Turn-

around.

Features

◆◆

◆

256K x 36, 512K x 18 memory configurations

◆◆

◆

Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

◆◆

◆

ZBT

Feature - No dead cycles between write and read cycles

◆◆

◆

Internally synchronized output buffer enable eliminates the

need to control OE

◆◆

◆

Single R/W (READ/WRITE) control pin

◆◆

◆

Positive clock-edge triggered address, data, and control signal

registers for fully pipelined applications

◆◆

◆

4-word burst capability (interleaved or linear)

◆◆

◆

Individual byte write (BW1 - BW4) control (May tie active)

◆◆

◆

Three chip enables for simple depth expansion

◆◆

◆

3.3V power supply (±5%)

◆◆

◆

3.3V I/O Supply (VDDQ)

◆◆

◆

Power down controlled by ZZ input

◆◆

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array(fBGA).

-A

Address Inputs Input Synchronous

, CE

Chip Enables Input Synchronous

Output Enable Input Asynchronous

R/W Read/Write Signal Input Synchronous

CEN

Clock Enable Input Synchronous

, BW

Individual Byte Write Selects Input Synchronous

CLK Clock Input N/A

ADV/LD Advance burst address / Load new address Input Synchronous

LBO

Linear / Interleaved Burst Order Input Static

ZZ Sleep Mode Input Asynchronous

I/O

-I/O

, I/O

-I/O

Data Input / Output I/O Synchronous

, V

DDQ

Core Power, I/O Power Supply Static

Ground Supply Static

5304 tbl 01

256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

ZBT™ Feature

3.3V I/O, Burst Counter

Pipelined Outputs

IDT71V65603/Z

IDT71V65803/Z

Address and control signals are applied to the SRAM during one clock

cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71V65603/5803 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803

to be suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE1, CE2, CE2) that allow the user

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed. The data bus will tri-state two cycles after chip is deselected

or a write is initiated.

The IDT71V65603/5803 have an on-chip burst counter. In the burst

mode, the IDT71V65603/5803 can provide four cycles of data for a

single address presented to the SRAM. The order of the burst

sequence is defined by the LBO input pin. The LBO pin selects

between linear and interleaved burst sequence. The ADV/LD signal is

used to load a new external address (ADV/LD = LOW) or increment

the internal burst counter (ADV/LD = HIGH).

The IDT71V65603/5803 SRAM utilize IDT's latest high-performance

CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array (fBGA) .

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

6.422

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with

ZBT

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol Pin Function I/O Active Description

-A

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the

rising edge of CLK, ADV/LD low, CEN low, and true chip enables.

ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address

and control when it is sampled low at the rising edge of clock with the chip selected. When

ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD

is sampled high then the internal burst counter is advanced for any burst that was in

progress. The external addresses are ignored when ADV/LD is sampled high.

R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a

Read or Write access to the memory array. The data bus activity for the current cycle takes

place two clock cycles later.

CEN

Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous

inputs, including clock are ignored and outputs remain unchanged. The effect of CEN

sampled high on the device outputs is as if the low to high clock transition did not occur.

For normal operation, CEN must be sampled low at rising edge of clock.

-BW

Individual Byte

Write Enables

I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.

On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write

signal (BW

-BW

) must be valid. The byte write signal must also be valid on each cycle of

a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate

byte(s) of data are written into the device two cycles later. BW

-BW

can all be tied low if

always doing write to the entire 36-bit word.

, CE

Chip Enables I LOW Synchronous active low chip enable. CE

and CE

are used with CE

to enable the

IDT71V65603/5803. (CE

or CE

sampled high or CE

sampled low) and ADV/LD low at the

rising edge of clock, initiates a deselect cycle. The ZBT

has a two cycle deselect, i.e.,

the data bus will tri-state two clock cycles after deselect is initiated.

Chip Enable I HIGH Synchronous active high chip enable. CE

is used with CE

and CE

to enable the chip.

has inverted polarity but otherwise identical to CE

and CE

CLK Clock I N/A This is the clock input to the IDT71V65603/5803. Except for OE, all timing references for the

device are made with respect to the rising edge of CLK.

I/O

-I/O

I/O

-I/O

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

LBO

Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected.

When LBO is low the Linear burst sequence is selected. LBO is a static input and it must

not change during device operation.

Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V65603/5803. When

OE is high the I/O pins are in a high-impedance state. OE does not need to be actively

controlled for read and write cycles. In normal operation, OE can be tied low.

ZZ Sleep Mode I N/A Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

71V65603/5803 to its lowest power consumption level. Data retention is guaranteed in

Sleep Mode.

Power Supply N/A N/A 3.3V core power supply.

DDQ

Power Supply N/A N/A 3.3V I/O Supply.

Ground N/A N/A Ground.

5304tbl 02

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

ZBT

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

Clk

Address A [0:18]

Control Logic

Address

Control

DI DO

Input Register

5304 drw 01

Clock

Data I/O [0:15],

I/O P[1:2]

Clk

Output Register

Mux

Sel

Gate

O E

C E1, CE2, C E2

R/W

C EN

ADV/LD

BW x

LB O

512x18 BIT

MEMORY ARRAY

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

71V65603S100PFG

Mfr. #:

Buy 71V65603S100PFG

Manufacturer:

IDT

Description:

SRAM 9M ZBT SLOW X36 P/L 3.3V

Lifecycle:

New from this manufacturer.

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71V65603S100PFG

71V65603S100PFG

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