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71V65603S100PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
6.4216
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT
™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The
specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a
Max. parameter (worse case at 70 deg. C, 3.135V).
6. Commercial temperature range only.
150MHz
(6)
133MHz 100MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
CY C
Clock Cycle Time 6.7
____
7.5
____
10
____
ns
t
F
(1 )
Clock Frequency
____
150
____
133
____
100 MHz
t
CH
(2 )
Clock High Pulse Width 2.0
____
2.2
____
3.2
____
ns
t
CL
(2 )
Clock Low Pulse Width 2.0
____
2.2
____
3.2
____
ns
Output Parameters
t
CD
Clock High to Valid Data
____
3.8.
____
4.2
____
5ns
t
CDC
Clock High to Data Change 1.5
____
1.5
____
1.5
____
ns
t
CL Z
(3 , 4,5)
Clock High to Output Active 1.5
____
1.5
____
1.5
____
ns
t
CHZ
(3 , 4, 5)
Clock High to Data High-Z 1.5 3 1.5 3 1.5 3.3 ns
t
OE
Output Enable Access Time
____
3.8
____
4.2
____
5ns
t
OLZ
(3,4)
Output Enable Low to Data Active 0
____
0
____
0
____
ns
t
OHZ
(3,4)
Output Enable High to Data High-Z
____
3.8
____
4.2
____
5ns
Set Up Times
t
SE
Clock Enable Setup Time 1.5
____
1.7
____
2.0
____
ns
t
SA
Address Setup Time 1.5
____
1.7
____
2.0
____
ns
t
SD
Data In Setup Time 1.5
____
1.7
____
2.0
____
ns
t
SW
Read/Write (R/W) Setup Time 1.5
____
1.7
____
2.0
____
ns
t
SADV
Advance/Load (ADV/LD) Setup Time 1.5
____
1.7
____
2.0
____
ns
t
SC
Chip Enable/Select Setup Time 1.5
____
1.7
____
2.0
____
ns
t
SB
Byte Write Enable (BWx) Setup Time 1.5
____
1.7
____
2.0
____
ns
Hold Times
t
HE
Clock Enable Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HA
Address Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HW
Read/Write (R/W) Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HADV
Advance/Load (ADV/LD) Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HB
Byte Write Enable (BWx) Hold Time 0.5
____
0.5
____
0.5
____
ns
5304 tbl 24
6.42
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT
™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
17
Timing Waveform of Read Cycle
(1,2,3,4)
NOTES:
1. Q (A
1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A
2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control
are loaded into the SRAM.
A
D
V
/
L
D
(
C
E
N
h
i
g
h
,
e
l
i
m
i
n
a
t
e
s
c
u
r
r
e
n
t
L
-
H
c
l
o
c
k
e
d
g
e
)
O
2
(
A
2
)
t
C
D
t
H
A
D
V
P
i
p
e
l
i
n
e
R
e
a
d
(
B
u
r
s
t
W
r
a
p
s
a
r
o
u
n
d
t
o
i
n
i
t
i
a
l
s
t
a
t
e
)
t
C
D
C
t
C
L
Z
t
C
H
Z
t
C
D
t
C
D
C
R
/
W
C
L
K
C
E
N
A
D
D
R
E
S
S
O
E
D
A
T
A
O
U
T
t
H
E
t
S
E
A
1
A
2
O
1
(
A
2
)
O
1
(
A
2
)
t
C
H
t
C
L
t
C
Y
C
t
S
A
D
V
t
H
W
t
S
W
t
H
A
t
S
A
t
H
C
t
S
C
B
u
r
s
t
P
i
p
e
l
i
n
e
R
e
a
d
P
i
p
e
l
i
n
e
R
e
a
d
B
W
1
-
B
W
4
5
3
0
4
d
r
w
0
6
C
E
1
,
C
E
2
(
2
)
Q
(
A
2
+
3
)
Q
(
A
2
)
Q
(
A
2
+
2
)
Q
(
A
2
+
2
)
Q
(
A
2
+
1
)
Q
(
A
2
)
Q
(
A
1
)
,
6.4218
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT
™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. D (A
1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A
2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Write Cycles
(1,2,3,4,5)
t
H
E
t
S
E
R
/W
A
1
A
2
C
L
K
C
E
N
A
D
V
/L
D
A
D
D
R
E
S
S
O
E
D
A
T
A
I
N
t
H
D
t
S
D
t
C
H
t
C
L
t
C
Y
C
t
H
A
D
V
t
S
A
D
V
t
H
W
t
S
W
t
H
A
t
S
A
t
H
C
t
S
C
B
u
r
s
t
P
ip
e
lin
e
W
r
it
e
P
ip
e
lin
e
W
rite
P
ip
e
lin
e
W
r
ite
t
H
B
t
S
B
(
B
u
r
s
t
W
r
a
p
s
a
r
o
u
n
d
to
in
itia
l
s
ta
te
)
t
H
D
t
S
D
(
C
E
N
h
ig
h
,
e
lim
in
a
t
e
s
c
u
r
re
n
t
L
-H
c
lo
c
k
e
d
g
e
)
(
2
)
D
(
A
2
+
2
)
D
(
A
2
+
3
)
D
(
A
1
)
D
(
A
2
)
D
(
A
2
)
5
3
0
4
d
r
w
0
7
B
W
1
-
B
W
4
C
E
1
,
C
E
2
D
(
A
2
+
1
)
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

71V65603S100PFG

Mfr. #:
Buy 71V65603S100PFG
Manufacturer:
IDT
Description:
SRAM 9M ZBT SLOW X36 P/L 3.3V
Lifecycle:
New from this manufacturer.
Delivery:
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