6.42
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used
(1)
Write Operation with Clock Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE
1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
CycleAddressR/W ADV/LD
CE
(2)
CEN BWx OE
I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Clock n+1 Ignored
n+2 A
1
H L LLXXXClock Valid
n+3 X X X X H X L Q
0
Clock Ignored, Data Q
0
is on the bus.
n+4 X X X X H X L Q
0
Clock Ignored, Data Q
0
is on the bus.
n+5 A
2
HL LLXLQ
0
Address A
0
Read out (bus trans.)
n+6 A
3
HL LLXLQ
1
Address A
1
Read out (bus trans.)
n+7 A
4
HL LLXLQ
2
Address A2 Read out (bus trans.)
5304 tbl 17
CycleAddressR/W ADV/LD
CE
(2)
CEN BWx OE
I/O Comments
nA
0
L L L L L X X Address and Control meet setup.
n+1 X X X X H X X X Clock n+1 Ignored.
n+2 A
1
L L L L L X X Clock Valid.
n+3 X X X X H X X X Clock Ignored.
n+4 X X X X H X X X Clock Ignored.
n+5 A
2
LLLLLXD
0
Write Data D
0
n+6 A
3
LLLLLXD
1
Write Data D
1
n+7 A
4
LLLLLXD
2
Write Data D
2
5304 tbl 18
6.4214
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation with Chip Enable Used
(1)
Write Operation with Chip Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/W ADV/LD
CE
(2 )
CEN BWx OE
I/O
(3 )
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
HL LLXLQ
0
Address A
0
Read out. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X L Q
1
Address A
1
Read out. Deselected.
n+7 A
2
H L L L X X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X L Q
2
Address A
2
Read out. Deselected.
5304 tbl 19
CycleAddressR/W ADV/LD
CE
(2)
CEN BWx OE
I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
L L LLLXD
0
Address D
0
Write in. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X X D
1
Address D
1
Write in. Deselected.
n+7 A
2
L L L L L X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X X D
2
Address D
2
Write in. Deselected.
5304 tbl 20
6.42
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
15
1
2
3
4
20 30 50 100 200
ΔtCD
(Typical, ns)
Capacitance (pF)
80
5
6
5304 drw 05
,
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
AC Test Conditions
(VDDQ = 3.3V)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(VDD = 3.3V +/-5%)
Figure 1. AC Test Load
AC Test Load
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to Vss if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leakage Current V
DD
= Max., V
IN
= 0V to V
DD
___
A
|I
LI
|
LBO Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
A
VO
L
Output Low Voltage I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -8mA, V
DD
= Min. 2.4
___
V
5304 tbl 21
Symbol Parameter Test Conditions
150MHz 133MHz 100MHz Unit
Com'l Ind Com'l Ind Com'l Ind
I
DD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2 )
325 345 300 320 250 270
mA
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = 0
(2,3)
40 60 40 60 40 60
mA
I
SB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = f
MAX
(2.3)
120 140 110 130 100 120
mA
I
SB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN >
V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
40 60 40 60 40 60
mA
I
ZZ
Full Sleep Mode
Supply Current
Device Selected, Outputs Open
CEN V
IL
, V
DD
= Max., ZZ V
HD
V
IN
V
HD
or
V
LD
, f = fMax
(2, 3)
40 60 40 60 40 60 mA
5304 tbl 22
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figure 1
5304 tbl 23
V
DDQ
/2
50
Ω
I/O
Z
0
=50
Ω
5304 drw 04
,

71V65603S100PFG

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 9M ZBT SLOW X36 P/L 3.3V
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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