6.426
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT
™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Pin Configuration - 512K x 18
119 BGA Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary; however,
the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp
up.
7. During production testing, the case temperature equals TA.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating
Commercial &
Industrial
Unit
V
TE R M
(2 )
Terminal Voltage with
Respect to GND
-0.5 to +4.6 V
V
TE R M
(3,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DD
V
V
TE R M
(4,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DD
+0.5 V
V
TE R M
(5,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DDQ
+0.5 V
T
A
(7)
Commercial
Operating Temperature
-0 to +70
o
C
Industrial
Operating Temperature
-40 to +85
o
C
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-55 to +125
o
C
P
T
Power Dissipation 2.0 W
I
OUT
DC Output Current 50 mA
5304 tbl 06
Symbol Parameter
(1 )
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 5 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
5304 tbl 07
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
C
E
1
C
E
2
N
C
N
C
B
W
2
B
W
1
C
E
2
V
D
D
V
S
S
C
L
K
R
/
W
C
E
N
O
E
A
D
V
/
L
D
N
C
(
2
)
A
1
8
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
N
U
(
3
)
D
N
U
(
3
)
D
N
U
(
3
)
D
N
U
(
3
)
L
B
O
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
V
D
D
V
S
S
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5304 drw 02a
V
DD
(1)
NC
NC
V
DD
(1)
NC
A
1
6
A
1
7
NC
V
DD
(1)
A
10
ZZ
,
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the
input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG
pins: TMS, TDI, TDO and TCK. The current die revision allows these pins to be
left unconnected, tied LOW (VSS), or tied HIGH (VDD).
Symbol Parameter
(1 )
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 7 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
5304 tbl 07a
100 TQFP Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV TBD pF
C
I/O
I/O Capacitance V
OUT
= 3dV TBD pF
5304 tbl 07b
165 fBGA Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
