FEBRUARY 2009
1
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT723616
CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING AND
BYTE SWAPPING 64 x 36 x 2
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
©
DSC-3107/3
FEATURES:
••
••
• Two independent FIFOs (64 X 36 storage capacity each) buffer
data between bidirectional 36-bit port A and two unidirectional
18/9-bit ports (Port B transmits, Port C receives)
••
••
• Clock frequencies up to 67 MHz (10 ns access time)
Free-running clock lines for each port: CLKA, CLKB and CLKC,
may be asynchronous or coincident (simultaneous reading and
writing of data is permitted)
••
••
• IDT Standard timing
••
••
• Empty flag functions: EFA (synchronized by CLKA) and EFB
(synchronized by CLKB)
••
••
• Full flag functions: FFA (synchronized by CLKA) and FFC
(synchronized by CLKC)
••
••
• Programmable Almost-Empty and Almost-Full flags; each has
four default offsets (4, 8, 12 and 16)
••
••
• Bus sizing of 18-bits (word) and 9-bits (byte) for ports B and C
••
••
• Byte order swapping on ports B and C
••
••
• Passive parity checking on ports A and C
••
••
• Parity generation can be selected for ports A and B
••
••
• Master Reset clears data and configures FIFO
••
••
• Width can be easily expanded by adding FIFOs
••
••
• Auto power down minimizes power dissipation
••
••
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
••
••
• High performance sub-micron CMOS technology
••
••
• Industrial temperature range (–40
o
C to +85
o
C) is available
••
••
• Green parts available, see ordering information
DESCRIPTION:
The IDT723616 is a monolithic, high-speed, low-power, CMOS Triple Bus
SyncFIFO™ (clocked) memory which supports clock frequencies up to 67
MHz and has read access times as fast as 10 ns. Two independent 64 x 36
dual-port SRAM FIFOs on board each chip buffer data between a bidirectional
36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data,
Port C receives data.) FIFO data can be read out of ports B and written into
port C using either 18-bit or 9-bit formats.
Reset (RST) initializes the read and write pointers to the first location of the
memory array and selects one of four possible default flag offset settings: 4, 8,
12 or 16.
Each FIFO has flags to indicate empty and full conditions and two program-
mable flags (Almost-Full and Almost-Empty) to indicate when a selected
Programmable Flag
Offset Registers
Input
Register
RAM
ARRAY
64 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
64 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
WENC
FIFO2,
FIFO1
Reset/
Control
Logic
RST
FIFO 1
FIFO 2
EFB
AEB
18
18
FFC
AFC
B
0
- B
17
FFA
AFA
FS0
FS1
EFA
AEA
3520 drw01
36
36
Bus Matching and
Byte Swapping
Output
Register
C
0
- C
17
CLKB
RENB
Port-B
Control
Logic
Common
Port
Control
Logic
(B and C)
SIZ0
SIZ1
CLKC
Parity
Generation
PGB
PEFC
PEFA
Parity
Generation
SWB0
SWB1
Parity
Check
Parity
check
PGA
Bus Matching and
Byte Swapping
A
0
- A
35
Port-C
Control
Logic
ODD/EVEN
SWC0
SWC1
FUNCTIONAL BLOCK DIAGRAM
