SWAP MODEDATA WRITTEN TO FIFO1READDATA READ FROM FIFO1
NO.
SWB1SWB0A35-A27A26-A18A17-A9A8-A0B17-B9B8-B0
1AB
LLABCD2C D
1DC
LHABCD2BA
1CD
HLABCD2AB
1BA
HHABCD2D C
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
™™
™™
™ WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
SWAP MODE DATA WRITTEN TO FIFO 1 READ
NO.
SWB1SWB0A35-A27A26-A18A17-A9A8-A0B17-B9
1A
2B
LLABCD3C
4D
1D
2C
LHABCD3B
4A
1C
2D
HLABCD3A
4B
1B
2A
HHABCD3D
4C
NOTE:
1. Unused bytes hold last FIFO1 output register data for byte-size reads.
EFB
RENB
CLKB
3520 drw10
HIGH
PGB,
ODD/
EVEN
B0-B8
Read 4
Read 1Read 3Previous DataRead 2
t
DIS
t
A
t
A
t
A
t
EN
t
PGH
t
PGS
t
A
t
ENH
t
SZS
t
SZH
t
ENS
DATA SWAP TABLE FOR BYTE READS FROM FIFO1
Figure 10. Port-B Byte Read Cycle Timing for FIFO1
DATA READ
FROM FIFO 1
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
™™
™™
™ WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2.Port-B size is word or byte; EFB is set LOW by the last word or byte read from FIFO1, respectively. (The word-size case is shown.)
Figure 12.
EFBEFB
EFBEFB
EFB
Flag Timing and First Data Read when FIFO1 is Empty
